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ddr3 sdram mt41j512m4 C 64 meg x 4 x 8 banks mt41j256m8 C 32 meg x 8 x 8 banks MT41J128M16 C 16 meg x 16 x 8 banks features ?v dd = v ddq = 1.5v 0.075v ? 1.5v center-terminated push/pull i/o ? differential bidirectional data strobe ?8 n -bit prefetch architecture ? differential clock inputs (ck, ck#) ? 8 internal banks ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? programmable cas read latency (cl) ? posted cas additive latency (al) ? programmable cas write latency (cwl) based on t ck ? fixed burst length (bl) of 8 and burst chop (bc) of 4 (via the mode register set [mrs]) ? selectable bc4 or bl8 on-the-fly (otf) ? self refresh mode ?t c of 0c to 95c C 64ms, 8192 cycle refresh at 0c to 85c C 32ms, 8192 cycle refresh at 85c to 95c ? self refresh temperature (srt) ? write leveling ? multipurpose register ? output driver calibration options 1 marking ? configuration C 512 meg x 4 512m4 C 256 meg x 8 256m8 C 128 meg x 16 128m16 ? fbga package (pb-free) C x4, x8 C 78-ball (8mm x 10.5mm) rev. h,m,j,k da C 78-ball (9mm x 11.5mm) rev. d hx ? fbga package (pb-free) C x16 C 96-ball (9mm x 14mm) rev. d ha C 96-ball (8mm x 14mm) rev. k jt ? timing C cycle time C 938ps @ cl = 14 (ddr3-2133) -093 C 1.071ns @ cl = 13 (ddr3-1866) -107 C 1.25ns @ cl = 11 (ddr3-1600) -125 C 1.5ns @ cl = 9 (ddr3-1333) -15e C 1.87ns @ cl = 7 (ddr3-1066) -187e ? operating temperature C commercial (0c t c +95c) none C industrial (C40c t c +95c) it ? revision :d/:h/:j/:k/ :m note: 1. not all options listed can be combined to define an offered product. use the part catalog search on http://www.micron.com for available offerings. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -093 1, 2, 3, 4 2133 14-14-14 13.09 13.09 13.09 -107 1, 2, 3 1866 13-13-13 13.91 13.91 13.91 -125 1, 2, 1600 11-11-11 13.75 13.75 13.75 -15e 1, 1333 9-9-9 13.5 13.5 13.5 -187e 1066 7-7-7 13.1 13.1 13.1 notes: 1. backward compatible to 1066, cl = 7 (-187e). 2. backward compatible to 1333, cl = 9 (-15e). 3. backward compatible to 1600, cl = 11 (-125). 4. backward compatible to 1866, cl = 13 (-107). 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. www.datasheet.co.kr datasheet pdf - http://www..net/
table 2: addressing parameter 512 meg x 4 256 meg x 8 128 meg x 16 configuration 64 meg x 4 x 8 banks 32 meg x 8 x 8 banks 16 meg x 16 x 8 banks refresh count 8k 8k 8k row addressing 32k (a[14:0]) 32k (a[14:0]) 16k (a[13:0]) bank addressing 8 (ba[2:0]) 8 (ba[2:0]) 8 (ba[2:0]) column addressing 2k (a[11, 9:0]) 1k (a[9:0]) 1k (a[9:0]) page size 1kb 1kb 2kb figure 1: ddr3 part numbers package 78-ball 9mm x 11.5mm fbga 78-ball 8mm x 10.5mm fbga 96-ball 9mm x 14mm fbga hx da ha example part number: mt41j256m8je-125:m 96-ball 8mm x 14mm fbga jt configuration 512 meg x 4 256 meg x 8 128 meg x 16 512m4 256m8 128m16 speed grade t ck = 1.071ns, cl = 13 t ck = 1.25ns, cl = 11 t ck = 1.5ns, cl = 9 t ck = 1.87ns, cl = 7 -107 -125 -15e -187e - configuration mt41j package speed revision t ck = 0.938ns, cl = 14 -093 revision :d/:h/:k/:m : temperature commercial industrial temperature ^ none it note: 1. not all options listed can be combined to define an offered product. use the part catalog search on http://www.micron.com for available offerings. fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on microns web site: http://www.micron.com . 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
contents state diagram ............................................................................................................................... ................. 11 functional description ............................................................................................................................... .... 12 industrial temperature ............................................................................................................................... 12 general notes ............................................................................................................................... ............. 12 functional block diagrams ............................................................................................................................. 1 4 ball assignments and descriptions ................................................................................................................. 16 package dimensions ............................................................................................................................... ........ 22 electrical specifications ............................................................................................................................... ... 26 absolute ratings ............................................................................................................................... .......... 26 input/output capacitance .......................................................................................................................... 27 thermal characteristics ............................................................................................................................... ... 28 electrical specifications C i dd specifications and conditions ............................................................................ 30 electrical characteristics C i dd specifications .................................................................................................. 41 electrical specifications C dc and ac .............................................................................................................. 45 dc operating conditions ........................................................................................................................... 45 input operating conditions ........................................................................................................................ 45 ac overshoot/undershoot specification ..................................................................................................... 48 slew rate definitions for single-ended input signals ................................................................................... 52 slew rate definitions for differential input signals ...................................................................................... 54 output driver impedance ............................................................................................................................... 55 34 ohm output driver impedance .............................................................................................................. 56 34 ohm driver ................................................................................................................. ........................... 57 34 ohm output driver sensitivity ................................................................................................................ 58 alternative 40 ohm driver .......................................................................................................................... 59 40 ohm output driver sensitivity ................................................................................................................ 59 output characteristics and operating conditions ............................................................................................ 61 reference output load ............................................................................................................................... 63 slew rate definitions for single-ended output signals ................................................................................. 64 slew rate definitions for differential output signals .................................................................................... 65 speed bin tables ............................................................................................................................... ............. 66 electrical characteristics and ac operating conditions ................................................................................... 71 command and address setup, hold, and derating ........................................................................................... 91 data setup, hold, and derating ....................................................................................................................... 99 commands C truth tables ............................................................................................................................. 1 08 commands ............................................................................................................................... .................... 111 deselect ............................................................................................................................... ................. 111 no operation ............................................................................................................................... ......... 111 zq calibration long ........................................................................................................................... 111 zq calibration short .......................................................................................................................... 111 activate ............................................................................................................................... .................. 111 read ............................................................................................................................... ......................... 111 write ............................................................................................................................... ....................... 112 precharge ............................................................................................................................... .............. 113 refresh ............................................................................................................................... ................... 113 self refresh ............................................................................................................................... ........... 114 dll disable mode ............................................................................................................................... ...... 115 input clock frequency change ...................................................................................................................... 119 write leveling ............................................................................................................................... ................ 121 write leveling procedure ........................................................................................................................... 123 write leveling mode exit procedure ........................................................................................................... 125 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
initialization ............................................................................................................................... .................. 126 mode registers ............................................................................................................................... ............... 128 mode register 0 (mr0) ............................................................................................................................... .... 129 burst length ............................................................................................................................... .............. 129 burst type ............................................................................................................................... .................. 130 dll reset ............................................................................................................................... ................. 131 write recovery ............................................................................................................................... ........... 131 precharge power-down (precharge pd) ...................................................................................................... 132 cas latency (cl) ............................................................................................................................... ........ 132 mode register 1 (mr1) ............................................................................................................................... .... 133 dll enable/disable .............................................................................................................................. 133 output drive strength ............................................................................................................................... 134 output enable/disable ...................................................................................................................... 134 tdqs enable ............................................................................................................................... ........... 134 on-die termination (odt) ........................................................................................................................ 135 write leveling ............................................................................................................................... ...... 135 posted cas additive latency (al) ............................................................................................................... 135 mode register 2 (mr2) ............................................................................................................................... .... 137 cas write latency (cwl) ........................................................................................................................ 137 auto self refresh (asr) ....................................................................................................................... 138 self refresh temperature (srt) ........................................................................................................ 138 srt versus asr ............................................................................................................................... ........... 139 dynamic on-die termination (odt) ......................................................................................................... 139 mode register 3 (mr3) ............................................................................................................................... .... 140 multipurpose register (mpr) ............................................................................................................ 140 mpr functional description ...................................................................................................................... 141 mpr address definitions and bursting order .............................................................................................. 142 mpr read predefined pattern .................................................................................................................... 147 mode register set (mrs) command ........................................................................................................ 147 zq calibration operation ......................................................................................................................... 148 activate operation ............................................................................................................................... ...... 149 read operation ............................................................................................................................... ............. 151 write operation ............................................................................................................................... ........... 162 dq input timing ............................................................................................................................... ........ 170 precharge operation ............................................................................................................................... .. 172 self refresh operation .............................................................................................................................. 172 extended temperature usage ........................................................................................................................ 174 power-down mode ............................................................................................................................... ......... 175 reset operation ............................................................................................................................... ............ 183 on-die termination (odt) ............................................................................................................................ 18 5 functional representation of odt ............................................................................................................. 185 nominal odt ............................................................................................................................... ............. 185 dynamic odt ............................................................................................................................... ................ 187 dynamic odt special use case ................................................................................................................. 187 functional description .............................................................................................................................. 187 synchronous odt mode ............................................................................................................................... . 193 odt latency and posted odt .................................................................................................................... 193 timing parameters ............................................................................................................................... ..... 193 odt off during reads .............................................................................................................................. 196 asynchronous odt mode .............................................................................................................................. 198 synchronous to asynchronous odt mode transition (power-down entry) .................................................. 200 asynchronous to synchronous odt mode transition (power-down exit) ........................................................ 202 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous to synchronous odt mode transition (short cke pulse) ...................................................... 204 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
list of figures figure 1: ddr3 part numbers .......................................................................................................................... 2 figure 2: simplified state diagram ................................................................................................................. 11 figure 3: 512 meg x 4 functional block diagram ............................................................................................. 14 figure 4: 256 meg x 8 functional block diagram ............................................................................................. 15 figure 5: 128 meg x 16 functional block diagram ........................................................................................... 15 figure 6: 78-ball fbga C x4, x8 (top view) ...................................................................................................... 16 figure 7: 96-ball fbga C x16 (top view) ......................................................................................................... 17 figure 8: 78-ball fbga C x4, x8 (da) ............................................................................................................... 22 figure 9: 78-ball fbga C x4, x8 (hx) ............................................................................................................... 23 figure 10: 96-ball fbga C x16 (ha) ................................................................................................................. 24 figure 11: 96-ball fbga C x16 (jt) .................................................................................................................. 25 figure 12: thermal measurement point ......................................................................................................... 29 figure 13: input signal ............................................................................................................................... ... 47 figure 14: overshoot ............................................................................................................................... ...... 48 figure 15: undershoot ............................................................................................................................... .... 48 figure 16: v ix for differential signals .............................................................................................................. 50 figure 17: single-ended requirements for differential signals ........................................................................ 50 figure 18: definition of differential ac-swing and t dvac ............................................................................... 51 figure 19: nominal slew rate definition for single-ended input signals .......................................................... 53 figure 20: nominal differential input slew rate definition for dqs, dqs# and ck, ck# .................................. 54 figure 21: output driver ............................................................................................................................... . 55 figure 22: dq output signal .......................................................................................................................... 62 figure 23: differential output signal .............................................................................................................. 63 figure 24: reference output load for ac timing and output slew rate ........................................................... 63 figure 25: nominal slew rate definition for single-ended output signals ....................................................... 64 figure 26: nominal differential output slew rate definition for dqs, dqs# .................................................... 65 figure 27: nominal slew rate and t vac for t is (command and address C clock) .............................................. 95 figure 28: nominal slew rate for t ih (command and address C clock) ............................................................ 96 figure 29: tangent line for t is (command and address C clock) ..................................................................... 97 figure 30: tangent line for t ih (command and address C clock) ..................................................................... 98 figure 31: nominal slew rate and t vac for t ds (dq C strobe) ......................................................................... 104 figure 32: nominal slew rate for t dh (dq C strobe) ...................................................................................... 105 figure 33: tangent line for t ds (dq C strobe) ................................................................................................ 106 figure 34: tangent line for t dh (dq C strobe) ............................................................................................... 107 figure 35: refresh mode ............................................................................................................................... 114 figure 36: dll enable mode to dll disable mode ........................................................................................ 116 figure 37: dll disable mode to dll enable mode ........................................................................................ 117 figure 38: dll disable t dqsck .................................................................................................................... 118 figure 39: change frequency during precharge power-down ........................................................................ 120 figure 40: write leveling concept ................................................................................................................. 121 figure 41: write leveling sequence ............................................................................................................... 124 figure 42: write leveling exit procedure ....................................................................................................... 125 figure 43: initialization sequence ................................................................................................................. 127 figure 44: mrs to mrs command timing ( t mrd) ......................................................................................... 128 figure 45: mrs to nonmrs command timing ( t mod) .................................................................................. 129 figure 46: mode register 0 (mr0) definitions ................................................................................................ 130 figure 47: read latency .............................................................................................................................. 132 figure 48: mode register 1 (mr1) definition ................................................................................................. 133 figure 49: read latency (al = 5, cl = 6) ....................................................................................................... 136 figure 50: mode register 2 (mr2) definition ................................................................................................. 137 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 51: cas write latency ...................................................................................................................... 138 figure 52: mode register 3 (mr3) definition ................................................................................................. 140 figure 53: mpr block diagram ...................................................................................................................... 141 figure 54: mpr system read calibration with bl8: fixed burst order single readout ..................................... 143 figure 55: mpr system read calibration with bl8: fixed burst order, back-to-back readout .......................... 144 figure 56: mpr system read calibration with bc4: lower nibble, then upper nibble .................................... 145 figure 57: mpr system read calibration with bc4: upper nibble, then lower nibble .................................... 146 figure 58: zq calibration timing (zqcl and zqcs) ................................................................................. 148 figure 59: example: meeting t rrd (min) and t rcd (min) ............................................................................. 149 figure 60: example: t faw ........................................................................................................................... .. 150 figure 61: read latency .............................................................................................................................. 151 figure 62: consecutive read bursts (bl8) .................................................................................................... 153 figure 63: consecutive read bursts (bc4) .................................................................................................... 153 figure 64: nonconsecutive read bursts ....................................................................................................... 154 figure 65: read (bl8) to write (bl8) .......................................................................................................... 154 figure 66: read (bc4) to write (bc4) otf .................................................................................................. 155 figure 67: read to precharge (bl8) .......................................................................................................... 155 figure 68: read to precharge (bc4) ......................................................................................................... 156 figure 69: read to precharge (al = 5, cl = 6) ........................................................................................... 156 figure 70: read with auto precharge (al = 4, cl = 6) ..................................................................................... 156 figure 71: data output timing C t dqsq and data valid window .................................................................... 158 figure 72: data strobe timing C reads ......................................................................................................... 159 figure 73: method for calculating t lz and t hz ............................................................................................... 160 figure 74: t rpre timing ............................................................................................................................... 160 figure 75: t rpst timing ............................................................................................................................... 161 figure 76: t wpre timing .............................................................................................................................. 163 figure 77: t wpst timing .............................................................................................................................. 163 figure 78: write burst ............................................................................................................................... . 164 figure 79: consecutive write (bl8) to write (bl8) ..................................................................................... 165 figure 80: consecutive write (bc4) to write (bc4) via otf ........................................................................ 165 figure 81: nonconsecutive write to write ................................................................................................. 166 figure 82: write (bl8) to read (bl8) .......................................................................................................... 166 figure 83: write to read (bc4 mode register setting) ................................................................................. 167 figure 84: write (bc4 otf) to read (bc4 otf) ........................................................................................... 168 figure 85: write (bl8) to precharge ........................................................................................................ 169 figure 86: write (bc4 mode register setting) to precharge ...................................................................... 169 figure 87: write (bc4 otf) to precharge ................................................................................................ 170 figure 88: data input timing ........................................................................................................................ 171 figure 89: self refresh entry/exit timing ...................................................................................................... 173 figure 90: active power-down entry and exit ................................................................................................ 177 figure 91: precharge power-down (fast-exit mode) entry and exit ................................................................. 178 figure 92: precharge power-down (slow-exit mode) entry and exit ................................................................ 178 figure 93: power-down entry after read or read with auto precharge (rdap) ............................................. 179 figure 94: power-down entry after write .................................................................................................... 179 figure 95: power-down entry after write with auto precharge (wrap) ........................................................ 180 figure 96: refresh to power-down entry .................................................................................................... 180 figure 97: activate to power-down entry ................................................................................................... 181 figure 98: precharge to power-down entry ............................................................................................... 181 figure 99: mrs command to power-down entry ........................................................................................... 182 figure 100: power-down exit to refresh to power-down entry ....................................................................... 182 figure 101: reset sequence ......................................................................................................................... 184 figure 102: on-die termination ................................................................................................................... 185 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 103: dynamic odt: odt asserted before and after the write, bc4 .................................................... 190 figure 104: dynamic odt: without write command .................................................................................. 190 figure 105: dynamic odt: odt pin asserted together with write command for 6 clock cycles, bl8 ............ 191 figure 106: dynamic odt: odt pin asserted with write command for 6 clock cycles, bc4 .......................... 192 figure 107: dynamic odt: odt pin asserted with write command for 4 clock cycles, bc4 .......................... 192 figure 108: synchronous odt ...................................................................................................................... 194 figure 109: synchronous odt (bc4) ............................................................................................................. 195 figure 110: odt during reads .................................................................................................................... 197 figure 111: asynchronous odt timing with fast odt transition .................................................................. 199 figure 112: synchronous to asynchronous transition during precharge power-down (dll off ) entry ............ 201 figure 113: asynchronous to synchronous transition during precharge power-down (dll off ) exit ............... 203 figure 114: transition period for short cke low cycles with entry and exit period overlapping ..................... 205 figure 115: transition period for short cke high cycles with entry and exit period overlapping ................... 205 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
list of tables table 1: key timing parameters ....................................................................................................................... 1 table 2: addressing ............................................................................................................................... .......... 2 table 3: 78-ball fbga C x4, x8 ball descriptions .............................................................................................. 18 table 4: 96-ball fbga C x16 ball descriptions ................................................................................................. 20 table 5: absolute maximum ratings .............................................................................................................. 26 table 6: ddr3 input/output capacitance ...................................................................................................... 27 table 7: thermal characteristics .................................................................................................................... 28 table 8: timing parameters used for i dd measurements C clock units ............................................................ 30 table 9: i dd0 measurement loop ................................................................................................................... 31 table 10: i dd1 measurement loop .................................................................................................................. 32 table 11: i dd measurement conditions for power-down currents ................................................................... 33 table 12: i dd2n and i dd3n measurement loop ................................................................................................ 34 table 13: i dd2nt measurement loop .............................................................................................................. 34 table 14: i dd4r measurement loop ................................................................................................................ 35 table 15: i dd4w measurement loop ............................................................................................................... 36 table 16: i dd5b measurement loop ................................................................................................................ 37 table 17: i dd measurement conditions for i dd6 , i dd6et , and i dd8 .................................................................... 38 table 18: i dd7 measurement loop .................................................................................................................. 39 table 19: i dd maximum limits C die rev d ..................................................................................................... 41 table 20: i dd maximum limits C die rev h .................................................................................................... 42 table 21: i dd maximum limits C die rev j, m ................................................................................................. 43 table 22: i dd maximum limits C die rev k ..................................................................................................... 43 table 23: dc electrical characteristics and operating conditions ................................................................... 45 table 24: dc electrical characteristics and input conditions .......................................................................... 45 table 25: input switching conditions ............................................................................................................. 46 table 26: control and address pins ................................................................................................................ 48 table 27: clock, data, strobe, and mask pins .................................................................................................. 48 table 28: differential input operating conditions (ck, ck# and dqs, dqs#) .................................................. 49 table 29: allowed time before ringback ( t dvac) for ck - ck# and dqs - dqs# ............................................... 51 table 30: single-ended input slew rate definition .......................................................................................... 52 table 31: differential input slew rate definition ............................................................................................. 54 table 32: 34 ohm driver impedance characteristics ....................................................................................... 56 table 33: 34 ohm driver pull-up and pull-down impedance calculations ....................................................... 57 table 34: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.5v ................................................................ 57 table 35: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.575v ............................................................. 57 table 36: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.425v ............................................................. 58 table 37: 34 ohm output driver sensitivity definition .................................................................................... 58 table 38: 34 ohm output driver voltage and temperature sensitivity .............................................................. 58 table 39: 40 ohm driver impedance characteristics ....................................................................................... 59 table 40: 40 ohm output driver sensitivity definition .................................................................................... 59 table 41: 40 ohm output driver voltage and temperature sensitivity .............................................................. 60 table 42: single-ended output driver characteristics ..................................................................................... 61 table 43: differential output driver characteristics ........................................................................................ 62 table 44: single-ended output slew rate definition ....................................................................................... 64 table 45: differential output slew rate definition .......................................................................................... 65 table 46: ddr3-1066 speed bins ................................................................................................................... 66 table 47: ddr3-1333 speed bins ................................................................................................................... 67 table 48: ddr3-1600 speed bins ................................................................................................................... 68 table 49: ddr3-1866 speed bins ................................................................................................................... 69 table 50: ddr3-2133 speed bins ................................................................................................................... 70 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions .................................................................... 71 table 52: electrical characteristics and ac operating conditions for speed extensions .................................... 81 table 53: command and address setup and hold values referenced C ac/dc-based ...................................... 91 table 54: derating values for t is/ t ih C ac175/dc100-based ............................................................................ 92 table 55: derating values for t is/ t ih C ac150/dc100-based ............................................................................ 92 table 56: derating values for t is/ t ih C ac135/dc100-based ............................................................................ 93 table 57: derating values for t is/ t ih C ac125/dc100-based ............................................................................ 93 table 58: minimum required time t vac above v ih(ac) or below v il(ac) for valid transition ............................... 94 table 59: ddr3 data setup and hold values at 1 v/ns (dqs, dqs# at 2 v/ns) C ac/dc-based .......................... 99 table 60: derating values for t ds/ t dh C ac175/dc100-based ........................................................................ 100 table 61: derating values for t ds/ t dh C ac150/dc100-based ........................................................................ 100 table 62: derating values for t ds/ t dh C ac135/dc100-based at 1v/ns ........................................................... 101 table 63: derating values for t ds/ t dh C ac135/dc100-based at 2v/ns ........................................................... 102 table 64: required minimum time t vac above v ih(ac) (below v il(ac) ) for valid dq transition ......................... 103 table 65: truth table C command ................................................................................................................. 108 table 66: truth table C cke .......................................................................................................................... 110 table 67: read command summary ............................................................................................................ 112 table 68: write command summary .......................................................................................................... 112 table 69: read electrical characteristics, dll disable mode ......................................................................... 118 table 70: write leveling matrix ..................................................................................................................... 122 table 71: burst order ............................................................................................................................... ..... 131 table 72: mpr functional description of mr3 bits ........................................................................................ 141 table 73: mpr readouts and burst order bit mapping ................................................................................... 142 table 74: self refresh temperature and auto self refresh description ............................................................ 174 table 75: self refresh mode summary ........................................................................................................... 174 table 76: command to power-down entry parameters .................................................................................. 175 table 77: power-down modes ....................................................................................................................... 176 table 78: truth table C odt (nominal) ......................................................................................................... 186 table 79: odt parameters ............................................................................................................................ 18 6 table 80: write leveling with dynamic odt special case .............................................................................. 187 table 81: dynamic odt specific parameters ................................................................................................. 188 table 82: mode registers for r tt,nom ............................................................................................................. 188 table 83: mode registers for r tt(wr) ............................................................................................................. 189 table 84: timing diagrams for dynamic odt ................................................................................................ 189 table 85: synchronous odt parameters ........................................................................................................ 194 table 86: asynchronous odt timing parameters for all speed bins ............................................................... 199 table 87: odt parameters for power-down (dll off ) entry and exit transition period ................................... 201 2gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
state diagram figure 2: simplified state diagram srx = self refresh exit write = wr, wrs4, wrs8 write ap = wrap, wraps4, wraps8 zqcl = zq long calibration zqcs = zq short calibration bank active reading writing activating refreshing self refresh idle active power- down zq calibration from any state power applied reset procedure power on initial- ization mrs, mpr, write leveling precharge power- down writing reading automatic sequence command sequence precharging read read read read ap read ap read ap pre, prea pre, prea pre, prea write write cke l cke l cke l write write ap write ap write ap pde pde pdx pdx srx sre ref mrs act reset zqcl zqcl/zqcs act = activate mpr = multipurpose register mrs = mode register set pde = power-down entry pdx = power-down exit pre = precharge prea = precharge all read = rd, rds4, rds8 read ap = rdap, rdaps4, rdaps8 ref = refresh reset = start reset procedure sre = self refresh entry 2gb: x4, x8, x16 ddr3 sdram state diagram pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
functional description ddr3 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is an 8 n -prefetch architecture with an interface de- signed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr3 sdram effectively consists of a single 8 n -bit-wide, four-clock- cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one- half-clock-cycle data transfers at the i/o pins. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. the ddr3 sdram operates from a differential clock (ck and ck#). the crossing of ck going high and ck# going low is referred to as the positive edge of ck. control, com- mand, and address signals are registered at every positive edge of ck. input data is reg- istered on the first rising edge of dqs after the write preamble, and output data is ref- erenced on the first rising edge of dqs after the read preamble. read and write accesses to the ddr3 sdram are burst-oriented. accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the ad- dress bits registered coincident with the read or write commands are used to select the bank and the starting column location for the burst access. the device uses a read and write bl8 and bc4. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdram, the pipelined, multibank architecture of ddr3 sdram allows for concurrent operation, thereby providing high bandwidth by hiding row pre- charge and activation time. a self refresh mode is provided, along with a power-saving, power-down mode. industrial temperature the industrial temperature (it) device requires that the case temperature not exceed C40c or 95c. jedec specifications require the refresh rate to double when t c exceeds 85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when t c is < 0c or >95c. general notes ? the functionality and the timing specifications discussed in this data sheet are for the dll enable mode of operation (normal operation). ? throughout this data sheet, various figures and text refer to dqs as dq. dq is to be interpreted as any and all dq collectively, unless specifically stated otherwise. ? the terms dqs and ck found throughout this data sheet are to be interpreted as dqs, dqs# and ck, ck# respectively, unless specifically stated otherwise. 2gb: x4, x8, x16 ddr3 sdram functional description pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
? complete functionality may be described throughout the document; any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all re- quirements. ? any specific requirement takes precedence over a general statement. ? any functionality not specifically stated is considered undefined, illegal, and not sup- ported, and can result in unknown operation. ? row addressing is denoted as a[ n :0] . for example, 1gb: n = 12 (x16); 1gb: n = 13 (x4, x8); 2gb: n = 13 (x16) and 2gb: n = 14 (x4, x8); 4gb: n = 14 (x16); and 4gb: n = 15 (x4, x8). ? dynamic odt has a special use case: when ddr3 devices are architected for use in a single rank memory array, the odt ball can be wired high rather than routed. refer to the dynamic odt special use case section. ? a x16 device's dq bus is comprised of two bytes. if only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: C connect udqs to ground via 1k * resistor. C connect udqs# to v dd via 1k * resistor. C connect udm to v dd via 1k * resistor. C connect dq[15:8] individually to either v ss , v dd , or v ref via 1k resistors,* or float dq[15:8]. *if odt is used, 1k resistor should be changed to 4x that of the selected odt. 2gb: x4, x8, x16 ddr3 sdram functional description pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
functional block diagrams ddr3 sdram is a high-speed, cmos dynamic random access memory. it is internally configured as an 8-bank dram. figure 3: 512 meg x 4 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 15 row- address mux control logic column- address counter/ latch mode registers 11 command decode a[14:0] ba[2:0] 15 address register 18 256 (x32) 8,192 i/o gating dm mask logic column decoder bank 0 memory array (32,768 x 256 x 32) bank 0 row- address latch and decoder 32,768 sense amplifiers bank control logic 18 bank 1 bank 2 bank 3 15 8 3 3 refresh counter 4 32 32 32 dqs, dqs# columns 0, 1, and 2 columns 0, 1, and 2 zqcl, zqcs to pullup/pulldown networks read drivers dq[3:0] read fifo and data mux data 4 3 bank 1 bank 2 bank 3 dm dm ck,ck# dqs, dqs# odt control zq cal we# zq rzq ck, ck# ras# cas# cs# odt cke reset# ck,ck# dll dq[3:0] (1 . . . 4) (1, 2) sw1 sw2 v ddq /2 r tt,nom r tt(wr) sw1 sw2 v ddq /2 r tt,nom r tt(wr) sw1 sw2 v ddq /2 r tt,nom r tt(wr) bc4 bc4 (burst chop) bc4 column 2 (select upper or lower nibble for bc4) data interface write drivers and input logic a12 v ssq otf otf 2gb: x4, x8, x16 ddr3 sdram functional block diagrams pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 4: 256 meg x 8 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 15 row- address mux control logic column- address counter/ latch mode registers 10 command decode a[14:0] ba[2:0] 15 18 8,192 i/o gating dm mask logic column decoder bank 0 memory array (32,768 x 128 x 64) bank 0 row- address latch and decoder 32,768 sense amplifiers bank control logic 18 bank 1 bank 2 bank 3 15 7 3 3 refresh counter 8 64 64 64 dqs, dqs# columns 0, 1, and 2 columns 0, 1, and 2 zqcl, zqcs to odt/output drivers read drivers dq[7:0] read fifo and data mux data 8 3 bank 1 bank 2 bank 3 dm/tdqs (shared pin) tdqs# ck, ck# dqs/dqs# zq cal zq rzq odt cke ck, ck# ras# we# cas# cs# reset# ck, ck# dll dq[7:0] dq8 (1 . . . 8) (1, 2) sw1 sw2 v ddq /2 r tt(wr) r tt,nom sw1 sw2 v ddq /2 r tt,nom r tt(wr) sw1 sw2 v ddq /2 r tt,nom r tt(wr) bc4 (burst chop) bc4 bc4 write drivers and input logic data interface column 2 (select upper or lower nibble for bc4) (128 x64) odt control address register a12 v ssq otf otf figure 5: 128 meg x 16 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 13 row- address mux control logic column- address counter/ latch mode registers 10 command decode a[13:0] ba[2:0] 14 address register 17 (128 x128) 16,384 i/o gating dm mask logic column decoder bank 0 memory array (16,384 x 128 x 128) bank 0 row- address latch and decoder 16,384 sense amplifiers bank control logic 17 bank 1 bank 2 bank 3 14 7 3 3 refresh counter 16 128 128 128 ldqs, ldqs#, udqs, udqs# column 0, 1, and 2 columns 0, 1, and 2 zqcl, zqcs to odt/output drivers bc4 read drivers dq[15:0] read fifo and data mux data 16 bc4 (burst chop) 3 bank 1 bank 2 bank 3 ldm/udm ck, ck# ldqs, ldqs# udqs, udqs# zq cal zq rzq odt cke ck, ck# ras# we# cas# cs# reset# ck, ck# dll dq[15:0] (1 . . . 16) (1 . . . 4) (1, 2) sw1 sw2 v ddq /2 bc4 sw1 sw2 v ddq /2 r tt,nom r tt(wr) sw1 sw2 column 2 (select upper or lower nibble for bc4) data interface write drivers and input logic odt control v ssq a12 otf otf v ddq /2 r tt,nom r tt(wr) r tt(wr) r tt,nom 2gb: x4, x8, x16 ddr3 sdram functional block diagrams pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
ball assignments and descriptions figure 6: 78-ball fbga C x4, x8 (top view) 1234 6789 5 v ss v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss v dd v ssq dq2 nf, dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# nc dq0 dqs dqs# nf, dq4 ras# cas# we# ba2 a0 a2 a9 a13 nf, nf/tdqs# dm, dm/tdqs dq1 v dd nf, dq7 ck ck# a10/ap nc a12/bc# a1 a11 a14 v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss v ss v ssq dq3 v ss nf, dq5 v ss v dd zq v refca ba1 a4 a6 a8 a b c d e f g h j k l m n notes: 1. ball descriptions listed in table 3 (page 18) are listed as x4, x8 if unique; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. example: d7 = nf, nf/tdqs#. nf applies to the x4 configuration only. nf/tdqs# applies to the x8 configuration onlyselectable between nf or tdqs# via mrs (symbols are de- fined in table 3). 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 7: 96-ball fbga C x16 (top view) 1234 6789 5 a b c d e f g h j k l m n p r t v ddq v ssq v ddq v ssq v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss dq13 v dd dq11 v ddq v ssq dq2 dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# dq15 v ss dq9 udm dq0 ldqs ldqs# dq4 ras# cas# we# ba2 a0 a2 a9 a13 dq12 udqs# udqs dq8 ldm dq1 v dd dq7 ck ck# a10/ap nc a12/bc# a1 a11 nc v ddq dq14 dq10 v ssq v ssq dq3 v ss dq5 v ss v dd zq v refca ba1 a4 a6 a8 v ss v ssq v ddq v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss note: 1. ball descriptions listed in table 4 (page 20). 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 3: 78-ball fbga C x4, x8 ball descriptions symbol type description a[14:13], a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4). see table 65 (page 108). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. the specific circuitry that is enabled/disabled is de- pendent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power- down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (excluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with the input data during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v refdq . dm has an optional use as tdqs on the x8. odt input on-die termination: odt enables (registered high) and disables (registered low) termination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[7:0], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input re- ceiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v ddq . reset# assertion and de-assertion are asynchronous. 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 3: 78-ball fbga C x4, x8 ball descriptions (continued) symbol type description dq[3:0] i/o data input/output: bidirectional data bus for the x4 configuration. dq[3:0] are referenced to v refdq . dq[7:0] i/o data input/output: bidirectional data bus for the x8 configuration. dq[7:0] are referenced to v refdq . dqs, dqs# i/o data strobe: output with read data. edge-aligned with read data. input with write data. center-aligned to write data. tdqs, tdqs# output termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. v dd supply power supply: 1.5v 0.075v. v ddq supply dq power supply: 1.5v 0.075v. isolated on the device for improved noise immuni- ty. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (excluding self refresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to external 240 resistor rzq, which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). nf C no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 4: 96-ball fbga C x16 ball descriptions symbol type description a13, a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also pro- vide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4). see table 65 (page 108). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. the specific circuitry that is enabled/disabled is de- pendent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle),or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self re- fresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (excluding cke and reset#) are disabled during self re- fresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the com- mand decoder. all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . ldm input input data mask: ldm is a lower-byte, input mask signal for write data. lower-byte input data is masked when ldm is sampled high along with the input data during a write access. although the ldm ball is input-only, the ldm loading is designed to match that of the dq and dqs balls. ldm is referenced to v refdq . odt input on-die termination: odt enables (registered high) and disables (registered low) termination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[15:0], ldqs, ldqs#, udqs, udqs#, ldm, and udm. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input re- ceiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v ddq . reset# assertion and de-assertion are asynchronous. 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 4: 96-ball fbga C x16 ball descriptions (continued) symbol type description udm input input data mask: udm is an upper-byte, input mask signal for write data. upper-byte input data is masked when udm is sampled high along with that input data during a write access. although the udm ball is input-only, the udm loading is designed to match that of the dq and dqs balls. udm is referenced to v refdq . dq[7:0] i/o data input/output: lower byte of bidirectional data bus for the x16 configuration. dq[7:0] are referenced to v refdq . dq[15:8] i/o data input/output: upper byte of bidirectional data bus for the x16 configuration. dq[15:8] are referenced to v refdq . ldqs, ldqs# i/o lower byte data strobe: output with read data. edge-aligned with read data. input with write data. center-aligned to write data. udqs, udqs# i/o upper byte data strobe: output with read data. edge-aligned with read data. input with write data. dqs is center-aligned to write data. v dd supply power supply: 1.5v 0.075v. v ddq supply dq power supply: 1.5v 0.075v. isolated on the device for improved noise immunity. v refca supply reference voltage for control, command, and address: v refca must be main- tained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (excluding self refresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to external 240 resistor rzq, which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). 2gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
package dimensions figure 8: 78-ball fbga C x4, x8 (da) ball a1 id 1.2 max 0.25 min 8 0.1 ball a1 id 78x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 0.8 typ 0.8 typ 9.6 ctr 10.5 0.1 0.8 0.05 0.155 1.8 ctr nonconductive overmold 0.12 a a seating plane 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l m n note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3 sdram package dimensions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 9: 78-ball fbga C x4, x8 (hx) 0.8 typ 9.6 ctr 11.5 0.1 0.8 typ 6.4 ctr 9 0.1 ball a1 id ball a1 id a b c d e f g h j k l m n 1 2 3 7 8 9 78x ?0.45 dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. a 0.12 a seating plane 1.1 0.1 0.25 min 1.8 ctr nonconductive overmold 0.155 note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3 sdram package dimensions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 10: 96-ball fbga C x16 (ha) ball a1 index dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 14 0.1 0.8 typ 1.1 0.1 12 ctr ball a1 index (covered by sr) 0.8 typ 9 0.1 0.25 min 6.4 ctr 96x ?0.45 9 8 7 3 2 1 a b c d e f g h j k l m n p r t a 0.12 a seating plane 1.8 ctr nonconductive overmold 0.155 note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3 sdram package dimensions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 11: 96-ball fbga C x16 (jt) ball a1 id 1.2 max 0.8 typ 8 0.15 0.8 0.1 seating plane a 12 ctr 6.4 ctr 0.12 a 96x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 14 0.15 ball a1 id 0.8 typ 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m n p r t note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3 sdram package dimensions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications absolute ratings stresses greater than those listed in table 5 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 5: absolute maximum ratings symbol parameter min max unit notes v dd v dd supply voltage relative to v ss C0.4 1.975 v 1 v ddq v dd supply voltage relative to v ssq C0.4 1.975 v v in , v out voltage on any pin relative to v ss C0.4 1.975 v t c operating case temperature - commercial 0 95 c 2, 3 operating case temperature - industrial C40 95 c 2, 3 operating case temperature - automotive C40 105 c 2, 3 t stg storage temperature C55 150 c notes: 1. v dd and v ddq must be within 300mv of each other at all times, and v ref must not be greater than 0.6 v ddq . when v dd and v ddq are <500mv, v ref can be 300mv. 2. max operating case temperature. t c is measured in the center of the package. 3. device functionality is not guaranteed if the dram device exceeds the maximum t c dur- ing operation. 2gb: x4, x8, x16 ddr3 sdram electrical specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
input/output capacitance table 6: ddr3 input/output capacitance note 1 applies to the entire table capacitance parameters symbol 800 1066 1333 1600 1866 2133 unit notes min max min max min max min max min max min max ck and ck# c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pf c: ck to ck# c dck 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf single-end i/o: dq, dm c io 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pf 2 differential i/o: dqs, dqs#, tdqs, tdqs# c io 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pf 3 c: dqs to dqs#, tdqs, tdqs# c ddqs 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 0 0.15 pf 3 c: dq to dqs c dio C0.5 0.3 C0.5 0.3 C0.5 0.3 C0.5 0.3 C0.5 0.3 C0.5 0.3 pf 4 inputs (ctrl, cmd, addr) c i 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pf 5 c: ctrl to ck c di_ctrl C0.5 0.3 C0.5 0.3 C0.4 0.2 C0.4 0.2 C0.4 0.2 C0.4 0.2 pf 6 c: cmd_addr to ck c di_cmd_ addr C0.5 0.5 C0.5 0.5 C0.4 0.4 C0.4 0.4 C0.4 0.4 C0.4 0.4 pf 7 zq pin capaci- tance c zq C 3.0 C 3.0 C 3.0 C 3.0 C 3.0 C 3.0 pf reset pin capaci- tance c re C 3.0 C 3.0 C 3.0 C 3.0 C 3.0 C 3.0 pf notes: 1. v dd = 1.5v 0.075mv, v ddq = v dd , v ref = v ss , f = 100 mhz, t c = 25c. v out(dc) = 0.5 v ddq , v out = 0.1v (peak-to-peak). 2. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 3. includes tdqs, tdqs#. c ddqs is for dqs vs. dqs# and tdqs vs. tdqs# separately. 4. c dio = c io(dq) - 0.5 (c io(dqs) + c io(dqs#) ). 5. excludes ck, ck#; ctrl = odt, cs#, and cke; cmd = ras#, cas#, and we#; addr = a[ n :0], ba[2:0]. 6. c di_ctrl = c i(ctrl) - 0.5 (c ck(ck) + c ck(ck#) ). 7. c di_cmd_addr = c i(cmd_addr) - 0.5 (c ck(ck) + c ck(ck#) ). 2gb: x4, x8, x16 ddr3 sdram electrical specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
thermal characteristics table 7: thermal characteristics parameter/condition value unit symbol notes operating case temperature - commercial 0 to +85 c t c 1, 2, 3 0 to +95 c t c 1, 2, 3, 4 operating case temperature - industrial -40 to +85 c t c 1, 2, 3 -40 to +95 c t c 1, 2, 3, 4 operating case temperature - automotive -40 to +85 c t c 1, 2, 3 -40 to +105 c t c 1, 2, 3, 4 junction-to-case (top) 96-ball (jt) tbd c/w jc 5 96-ball (ha) 3.9 78-ball (da), j:/:k tbd 78-ball (da), m 6.5 78-ball (hx) 3.9 notes: 1. maximum operating case temperature. t c is measured in the center of the package. 2. a thermal solution must be designed to ensure the dram device does not exceed t c max during operation. 3. device functionality is not guaranteed if the dram device exceeds t c max during oper- ation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of srt or asr (if available) must be enabled. 5. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 2gb: x4, x8, x16 ddr3 sdram thermal characteristics pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 12: thermal measurement point / / : : 7 f whvwsrlqw 2gb: x4, x8, x16 ddr3 sdram thermal characteristics pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications C i dd specifications and conditions within the following i dd measurement tables, the following definitions and conditions are used, unless stated otherwise: ? low: v in v il(ac)max ; high: v in v ih(ac)min . ? midlevel: inputs are v ref = v dd /2. ?r on set to rzq/7 (34 ?r tt,nom set to rzq/6 (40 ?r tt(wr) set to rzq/2 (120 ?q off is enabled in mr1. ? odt is enabled in mr1 (r tt,nom ) and mr2 (r tt(wr) ). ? tdqs is disabled in mr1. ? external dq/dqs/dm load resistor is 25 to v ddq /2. ? burst lengths are bl8 fixed. ? al equals 0 (except in i dd7 ). ?i dd specifications are tested after the device is properly initialized. ? input slew rate is specified by ac parametric test conditions. ? optional asr is disabled. ? read burst type uses nibble sequential (mr0[3] = 0). ? loop patterns must be executed at least once before current measurements begin. table 8: timing parameters used for i dd measurements C clock units i dd parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit -25e -25 -187e -187 -15e -15 -125e -125 -107 -093 5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 13-13-13 14-14-14 t ck (min) i dd 2.5 1.875 1.5 1.25 1.071 0.938 ns cl i dd 56789 10 10 11 13 14 ck t rcd (min) i dd 5 6 7 8 9 10 10 11 13 14 ck t rc (min) i dd 20 21 27 28 33 34 38 39 45 50 ck t ras (min) i dd 15 15 20 20 24 24 28 28 32 36 ck t rp (min) 5 6 7 8 9 10 10 11 13 14 ck t faw x4, x8 16 16 20 20 20 20 24 24 26 27 ck x16 20 20 27 27 30 30 32 32 33 38 ck t rrd i dd x4, x8 4 4 4 4 4 4 5 5 5 6 ck x16 4 4 6 6 5 5 6 6 6 7 ck t rfc 1gb 44 44 59 59 74 74 88 88 103 118 ck 2gb 64 64 86 86 107 107 128 128 150 172 ck 4gb 104 104 139 139 174 174 208 208 243 279 ck 8gb 140 140 187 187 234 234 280 280 328 375 ck 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 9: i dd0 measurement loop ck, ck# cke sub- loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data toggling static high 0 0 act 00110000000 C 1 d 10000000000 C 2 d 10000000000 C 3 d# 11110000000 C 4 d# 11110000000 C repeat cycles 1 through 4 until n ras - 1; truncate if needed n ras pre 00100000000 C repeat cycles 1 through 4 until n rc - 1; truncate if needed n rc act 001100000f0 C n rc + 1 d 100000000f0 C n rc + 2 d 100000000f0 C n rc + 3 d# 111100000f0 C n rc + 4 d# 111100000f0 C repeat cycles n rc + 1 through n rc + 4 until n rc - 1 + n ras -1; truncate if needed n rc + n ras pre 001000000f0 C repeat cycles n rc + 1 through n rc + 4 until 2 rc - 1; truncate if needed 1 2 n rc repeat sub-loop 0, use ba[2:0] = 1 2 4 n rc repeat sub-loop 0, use ba[2:0] = 2 3 6 n rc repeat sub-loop 0, use ba[2:0] = 3 4 8 n rc repeat sub-loop 0, use ba[2:0] = 4 5 10 n rc repeat sub-loop 0, use ba[2:0] = 5 6 12 n rc repeat sub-loop 0, use ba[2:0] = 6 7 14 n rc repeat sub-loop 0, use ba[2:0] = 7 notes: 1. dq, dqs, dqs# are midlevel. 2. dm is low. 3. only selected bank (single) active. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 10: i dd1 measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2 toggling static high 0 0 act 00110000000 C 1 d 10000000000 C 2 d 10000000000 C 3 d# 11110000000 C 4 d# 11110000000 C repeat cycles 1 through 4 until n rcd - 1; truncate if needed n rcd rd 0 1 0 1 0 0 0 0 0 0 0 00000000 repeat cycles 1 through 4 until n ras - 1; truncate if needed n ras pre 00100000000 C repeat cycles 1 through 4 until n rc - 1; truncate if needed n rc act 001100000f0 C n rc + 1 d 100000000f0 C n rc + 2 d 100000000f0 C n rc + 3 d# 111100000f0 C n rc + 4 d# 111100000f0 C repeat cycles n rc + 1 through n rc + 4 until n rc + n rcd - 1; truncate if needed n rc + n rcd rd 0 1 0 1 0 0 0 0 0 f 0 00110011 repeat cycles n rc + 1 through n rc + 4 until n rc + n ras - 1; truncate if needed n rc + n ras pre 001000000f0 C repeat cycle n rc + 1 through n rc + 4 until 2 n rc - 1; truncate if needed 1 2 n rc repeat sub-loop 0, use ba[2:0] = 1 2 4 n rc repeat sub-loop 0, use ba[2:0] = 2 3 6 n rc repeat sub-loop 0, use ba[2:0] = 3 4 8 n rc repeat sub-loop 0, use ba[2:0] = 4 5 10 n rc repeat sub-loop 0, use ba[2:0] = 5 6 12 n rc repeat sub-loop 0, use ba[2:0] = 6 7 14 n rc repeat sub-loop 0, use ba[2:0] = 7 notes: 1. dq, dqs, dqs# are midlevel unless driven as required by the rd command. 2. dm is low. 3. burst sequence is driven on each dq signal by the rd command. 4. only selected bank (single) active. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 11: i dd measurement conditions for power-down currents name i dd2p0 precharge power-down current (slow exit) 1 i dd2p1 precharge power-down current (fast exit) 1 i dd2q precharge quiet standby current i dd3p active power-down current timing pattern n/a n/a n/a n/a cke low low high low external clock toggling toggling toggling toggling t ck t ck (min) i dd t ck (min) i dd t ck (min) i dd t ck (min) i dd t rc n/a n/a n/a n/a t ras n/a n/a n/a n/a t rcd n/a n/a n/a n/a t rrd n/a n/a n/a n/a t rc n/a n/a n/a n/a cl n/a n/a n/a n/a al n/a n/a n/a n/a cs# high high high high command inputs low low low low row/column addr low low low low bank addresses low low low low dm low low low low data i/o midlevel midlevel midlevel midlevel output buffer dq, dqs enabled enabled enabled enabled odt 2 enabled, off enabled, off enabled, off enabled, off burst length 8 8 8 8 active banks none none none all idle banks all all all none special notes n/a n/a n/a n/a notes: 1. mr0[12] defines dll on/off behavior during precharge power-down only; dll on (fast exit, mr0[12] = 1) and dll off (slow exit, mr0[12] = 0). 2. enabled, off means the mr bits are enabled, but the signal is low. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 12: i dd2n and i dd3n measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data toggling static high 0 0 d 10000000000 C 1 d 10000000000 C 2 d# 111100000f0 C 3 d# 111100000f0 C 1 4C7 repeat sub-loop 0, use ba[2:0] = 1 2 8C11 repeat sub-loop 0, use ba[2:0] = 2 3 12C15 repeat sub-loop 0, use ba[2:0] = 3 4 16C19 repeat sub-loop 0, use ba[2:0] = 4 5 20C23 repeat sub-loop 0, use ba[2:0] = 5 6 24C27 repeat sub-loop 0, use ba[2:0] = 6 7 28C31 repeat sub-loop 0, use ba[2:0] = 7 notes: 1. dq, dqs, dqs# are midlevel. 2. dm is low. 3. all banks closed during i dd2n ; all banks open during i dd3n . table 13: i dd2nt measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data toggling static high 0 0 d 10000000000 C 1 d 10000000000 C 2 d# 111100000f0 C 3 d# 111100000f0 C 1 4C7 repeat sub-loop 0, use ba[2:0] = 1; odt = 0 2 8C11 repeat sub-loop 0, use ba[2:0] = 2; odt = 1 3 12C15 repeat sub-loop 0, use ba[2:0] = 3; odt = 1 4 16C19 repeat sub-loop 0, use ba[2:0] = 4; odt = 0 5 20C23 repeat sub-loop 0, use ba[2:0] = 5; odt = 0 6 24C27 repeat sub-loop 0, use ba[2:0] = 6; odt = 1 7 28C31 repeat sub-loop 0, use ba[2:0] = 7; odt = 1 notes: 1. dq, dqs, dqs# are midlevel. 2. dm is low. 3. all banks closed. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 14: i dd4r measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 rd 0 1 0 1 0 0 0 0 0 0 0 00000000 1 d 10000000000 C 2 d# 11110000000 C 3 d# 11110000000 C 4 rd 0 1 0 1 0 0 0 0 0 f 0 00110011 5 d 100000000f0 C 6 d# 111100000f0 C 7 d# 111100000f0 C 1 8C15 repeat sub-loop 0, use ba[2:0] = 1 2 16C23 repeat sub-loop 0, use ba[2:0] = 2 3 24C31 repeat sub-loop 0, use ba[2:0] = 3 4 32C39 repeat sub-loop 0, use ba[2:0] = 4 5 40C47 repeat sub-loop 0, use ba[2:0] = 5 6 48C55 repeat sub-loop 0, use ba[2:0] = 6 7 56C63 repeat sub-loop 0, use ba[2:0] = 7 notes: 1. dq, dqs, dqs# are midlevel when not driving in burst sequence. 2. dm is low. 3. burst sequence is driven on each dq signal by the rd command. 4. all banks open. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 15: i dd4w measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 wr 0 1 0 0 1 0 0 0 0 0 0 00000000 1 d 10001000000 C 2 d# 11111000000 C 3 d# 11111000000 C 4 wr 0 1 0 0 1 0 0 0 0 f 0 00110011 5 d 100010000f0 C 6 d# 111110000f0 C 7 d# 111110000f0 C 1 8C15 repeat sub-loop 0, use ba[2:0] = 1 2 16C23 repeat sub-loop 0, use ba[2:0] = 2 3 24C31 repeat sub-loop 0, use ba[2:0] = 3 4 32C39 repeat sub-loop 0, use ba[2:0] = 4 5 40C47 repeat sub-loop 0, use ba[2:0] = 5 6 48C55 repeat sub-loop 0, use ba[2:0] = 6 7 56C63 repeat sub-loop 0, use ba[2:0] = 7 notes: 1. dq, dqs, dqs# are midlevel when not driving in burst sequence. 2. dm is low. 3. burst sequence is driven on each dq signal by the wr command. 4. all banks open. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 16: i dd5b measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data toggling static high 0 0 ref 00010000000 C 1a 1 d 10000000000 C 2 d 10000000000 C 3 d# 111100000f0 C 4 d# 111100000f0 C 1b 5C8 repeat sub-loop 1a, use ba[2:0] = 1 1c 9C12 repeat sub-loop 1a, use ba[2:0] = 2 1d 13C16 repeat sub-loop 1a, use ba[2:0] = 3 1e 17C20 repeat sub-loop 1a, use ba[2:0] = 4 1f 21C24 repeat sub-loop 1a, use ba[2:0] = 5 1g 25C28 repeat sub-loop 1a, use ba[2:0] = 6 1h 29C32 repeat sub-loop 1a, use ba[2:0] = 7 2 33C n rfc - 1 repeat sub-loop 1a through 1h until n rfc - 1; truncate if needed notes: 1. dq, dqs, dqs# are midlevel. 2. dm is low. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 17: i dd measurement conditions for i dd6 , i dd6et , and i dd8 i dd test i dd6 : self refresh current normal temperature range t c = 0c to +85c i dd6et : self refresh current extended temperature range t c = 0c to +95c i dd8 : reset 2 cke low low midlevel external clock off, ck and ck# = low off, ck and ck# = low midlevel t ck n/a n/a n/a t rc n/a n/a n/a t ras n/a n/a n/a t rcd n/a n/a n/a t rrd n/a n/a n/a t rc n/a n/a n/a cl n/a n/a n/a al n/a n/a n/a cs# midlevel midlevel midlevel command inputs midlevel midlevel midlevel row/column addresses midlevel midlevel midlevel bank addresses midlevel midlevel midlevel data i/o midlevel midlevel midlevel output buffer dq, dqs enabled enabled midlevel odt 1 enabled, midlevel enabled, midlevel midlevel burst length n/a n/a n/a active banks n/a n/a none idle banks n/a n/a all srt disabled (normal) enabled (extended) n/a asr disabled disabled n/a notes: 1. enabled, midlevel means the mr command is enabled, but the signal is midlevel. 2. during a cold boot reset (initialization), current reading is valid after power is stable and reset has been low for 1ms; during a warm boot reset (while operating), current reading is valid after reset has been low for 200ns + t rfc. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 18: i dd7 measurement loop ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 act00110000000 C 1 rda01010001000 00000000 2 d 10000000000 C 3 repeat cycle 2 until n rrd - 1 1 n rrd act001101000f0 C n rrd + 1 rda 010101010f0 00110011 n rrd + 2 d 100001000f0 C n rrd + 3 repeat cycle n rrd + 2 until 2 n rrd - 1 2 2 n rrd repeat sub-loop 0, use ba[2:0] = 2 3 3 n rrd repeat sub-loop 1, use ba[2:0] = 3 4 4 n rrd d 100003000f0 C 4 n rrd + 1 repeat cycle 4 n rrd until n faw - 1, if needed 5 n faw repeat sub-loop 0, use ba[2:0] = 4 6 n faw + n rrd repeat sub-loop 1, use ba[2:0] = 5 7 n faw + 2 n rrd repeat sub-loop 0, use ba[2:0] = 6 8 n faw + 3 n rrd repeat sub-loop 1, use ba[2:0] = 7 9 n faw + 4 n rrd d 100007000f0 C n faw + 4 n rrd + 1 repeat cycle n faw + 4 n rrd until 2 n faw - 1, if needed 10 2 n faw act001100000f0 C 2 n faw + 1 rda010100010f0 00110011 2 n faw + 2 d 100000000f0 C 2 n faw + 3 repeat cycle 2 n faw + 2 until 2 n faw + n rrd - 1 11 2 n faw + n rrd act00110100000 C 2 n faw + n rrd + 1 rda 0 1010101000 00000000 2 n faw + n rrd + 2 d 1 0 000100000 C 2 n faw + n rrd + 3 repeat cycle 2 n faw + n rrd + 2 until 2 n faw + 2 n rrd - 1 12 2 n faw + 2 n rrd repeat sub-loop 10, use ba[2:0] = 2 13 2 n faw + 3 n rrd repeat sub-loop 11, use ba[2:0] = 3 14 2 n faw + 4 n rrd d 10000300000 C 2 n faw + 4 n rrd + 1 repeat cycle 2 n faw + 4 n rrd until 3 n faw - 1, if needed 15 3 n faw repeat sub-loop 10, use ba[2:0] = 4 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 18: i dd7 measurement loop (continued) ck, ck# cke sub-loop cycle number command cs# ras# cas# we# odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 3 toggling static high 16 3 n faw + n rrd repeat sub-loop 11, use ba[2:0] = 5 17 3 n faw + 2 n rrd repeat sub-loop 10, use ba[2:0] = 6 18 3 n faw + 3 n rrd repeat sub-loop 11, use ba[2:0] = 7 19 3 n faw + 4 n rrd d 10000700000 C 3 n faw + 4 n rrd + 1 repeat cycle 3 n faw + 4 n rrd until 4 n faw - 1, if needed notes: 1. dq, dqs, dqs# are midlevel unless driven as required by the rd command. 2. dm is low. 3. burst sequence is driven on each dq signal by the rd command. 4. al = cl-1. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C i dd specifications and conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics C i dd specifications i dd values are for full operating range of voltage and temperature unless otherwise no- ted. table 19: i dd maximum limits C die rev d speed bin ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit notes i dd width i dd0 x4 75 85 95 105 ma 1, 2 x8 75 85 95 105 ma x16 90 100 110 120 ma i dd1 x4 95 100 105 110 ma 1, 2 x8 95 100 105 110 ma x16 125 130 135 140 ma i dd2p0 (slow) all 12 12 12 12 ma 1, 2 i dd2p1 (fast) x4, x8 25 30 35 40 ma 1, 2 x16 30 35 40 45 ma i dd2q all 30 35 40 45 ma 1, 2 i dd2n all 32 37 42 47 ma 1, 2 i dd2nt x4, x8 40 45 50 55 ma 1, 2 x16 55 60 65 70 ma i dd3p x4, x8 30 35 40 45 ma 1, 2 x16 35 40 45 50 ma i dd3n all 35 40 45 50 ma 1, 2 i dd4r x4 125 145 165 185 ma 1, 2 x8 140 160 180 200 ma x16 200 245 270 295 ma i dd4w x4 135 155 170 190 ma 1, 2 x8 145 165 185 205 ma x16 210 255 280 315 ma i dd5b all 190 200 215 220 ma 1, 2 i dd6 all 12 12 12 12 ma 1, 2, 3 i dd6et all 15 15 15 15 ma 2, 4 i dd7 x4 335 385 435 485 ma 1, 2 x8 335 385 435 485 ma x16 375 425 475 525 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 1, 2 notes: 1. t c = 85c; srt and asr are disabled. 2. enabling asr could increase i dd x by up to an additional 2ma. 3. restricted to t c max = 85c. 4. t c = 85c; asr and odt are disabled; srt is enabled. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics C i dd specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
5. the i dd values must be derated (increased) on it-option devices when operated outside the range 0c t c +85c: 5a. when t c < 0c: i dd2p0 , i dd2p1 and i dd3p must be derated by 4%; i dd4r and i dd5w must be derated by 2%; and i dd6 , i dd6et and i dd7 must be derated by 7%. 5b. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 2%; and i dd2px must be derated by 30%. table 20: i dd maximum limits C die rev h speed bin ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit notes i dd width i dd0 all 70 75 80 88 ma 1, 2 i dd1 all 90 95 100 108 ma 1, 2 i dd2p0 (slow) all 12 12 12 14 ma 1, 2 i dd2p1 (fast) all 30 35 40 48 ma 1, 2 i dd2q all 35 40 45 53 ma 1, 2 i dd2n all 37 42 47 55 ma 1, 2 i dd2nt all 45 50 55 63 ma 1, 2 i dd3p all 40 45 50 58 ma 1, 2 i dd3n all 45 50 55 63 ma 1, 2 i dd4r x4 115 130 145 165 ma 1, 2 x8 130 145 160 180 ma i dd4w x4 115 130 145 165 ma 1, 2 x8 130 145 160 180 ma i dd5b all 185 190 195 205 ma 1, 2 i dd6 all 12 12 12 12 ma 1, 2, 3 i dd6et all 15 15 15 15 ma 2, 4 i dd7 all 230 245 260 280 ma 1, 2 i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 1, 2 notes: 1. t c = +85c; srt and asr are disabled. 2. enabling asr could increase i dd x by up to an additional 2ma. 3. restricted to t c max = +85c. 4. t c = +85c; asr and odt are disabled; srt is enabled. 5. the i dd values must be derated (increased) on it-option devices when operated outside the range 0c t c +85c: 5a. when t c < 0c: i dd2p0 , i dd2p1 and i dd3p must be derated by 4%; i dd4r and i dd5w must be derated by 2%; and i dd6 , i dd6et and i dd7 must be derated by 7%. 5b. when t c > +85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 2%; and i dd2px must be derated by 30%. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics C i dd specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 21: i dd maximum limits C die rev j, m speed bin ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit notes i dd width i dd0 all 60 65 70 75 ma 1, 2 i dd1 all 70 75 80 85 ma 1, 2 i dd2p0 (slow) all 12 12 12 12 ma 1, 2 i dd2p1 (fast) all 27 32 37 42 ma 1, 2 i dd2q all 30 35 40 45 ma 1, 2 i dd2n all 33 38 43 48 ma 1, 2 i dd2nt all 35 40 45 50 ma 1, 2 i dd3p all 40 45 50 55 ma 1, 2 i dd3n all 45 50 55 60 ma 1, 2 i dd4r x4 115 126 141 156 ma 1, 2 x8 130 141 156 171 ma i dd4w x4 100 115 130 145 ma 1, 2 x8 115 130 145 160 ma i dd5b all 185 190 195 200 ma 1, 2 i dd6 all 12 12 12 12 ma 1, 2, 3 i dd6et all 15 15 15 15 ma 2, 4 i dd7 all 210 225 240 255 ma 1, 2 i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 1, 2 notes: 1. t c = 85c; srt and asr are disabled. 2. enabling asr could increase i dd x by up to an additional 2ma. 3. restricted to t c max = 85c. 4. t c = 85c; asr and odt are disabled; srt is enabled. 5. the i dd values must be derated (increased) on it-option devices when operated outside the range 0c t c +85c: 5a. when t c < 0c: i dd2p0 , i dd2p1 and i dd3p must be derated by 4%; i dd4r and i dd5w must be derated by 2%; and i dd6 , i dd6et and i dd7 must be derated by 7%. 5b. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 2%; and i dd2px must be derated by 30%. table 22: i dd maximum limits C die rev k speed bin ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit notes i dd widt h i dd0 x4, x8 39 41 42 43 46 ma 1, 2 x16 46 48 49 51 55 ma i dd1 x4 46 50 52 55 57 ma 1, 2 x8 50 54 56 58 60 ma x16 62 67 69 72 75 ma 2gb: x4, x8, x16 ddr3 sdram electrical characteristics C i dd specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 22: i dd maximum limits C die rev k (continued) speed bin ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit notes i dd widt h i dd2p0 (slow) all 12 12 12 12 12 ma 1, 2 i dd2p1 (fast) all 15 15 15 15 15 ma 1, 2 i dd2q all 22 22 22 22 22 ma 1, 2 i dd2n all 23 23 23 23 23 ma 1, 2 i dd2nt x4,x8 29 32 34 36 40 ma 1, 2 x16 33 36 37 39 43 ma i dd3p all 22 22 22 22 22 ma 1, 2 i dd3n x4,x8 31 33 35 37 40 ma 1, 2 x16 33 36 37 39 43 ma i dd4r x4 70 84 96 106 120 ma 1, 2 x8 74 88 100 110 125 ma x16 95 115 135 155 180 ma i dd4w x4 75 87 99 110 122 ma 1, 2 x8 79 91 103 114 126 ma x16 107 127 146 164 184 ma i dd5b all 109 111 112 114 120 ma 1, 2 i dd6 all 12 12 12 12 12 ma 1, 2, 3 i dd6et all 15 15 15 15 15 ma 2, 4 i dd7 x4, x8 128 157 163 171 190 ma 1, 2 x16 159 179 202 226 248 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 1, 2 notes: 1. t c = 85c; srt and asr are disabled. 2. enabling asr could increase i dd x by up to an additional 2ma. 3. restricted to t c max = 85c. 4. t c = 85c; asr and odt are disabled; srt is enabled. 5. the i dd values must be derated (increased) on it-option devices when operated outside the range 0c t c +85c: 5a. when t c < 0c: i dd2p0 , i dd2p1 and i dd3p must be derated by 4%; i dd4r and i dd5w must be derated by 2%; and i dd6 , i dd6et and i dd7 must be derated by 7%. 5b. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 2%; and i dd2px must be derated by 30%. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics C i dd specifications pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications C dc and ac dc operating conditions table 23: dc electrical characteristics and operating conditions all voltages are referenced to v ss parameter/condition symbol min nom max unit notes supply voltage v dd 1.425 1.5 1.575 v 1, 2 i/o supply voltage v ddq 1.425 1.5 1.575 v 1, 2 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) i i C2 C 2 a v ref supply leakage current v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) i vref C1 C 1 a 4 notes: 1. v dd and v ddq must track one another. v ddq must be v dd . v ss = v ssq . 2. v dd and v ddq may include ac noise of 50mv (250 khz to 20 mhz) in addition to the dc (0 hz to 250 khz) specifications. v dd and v ddq must be at same level for valid ac timing parameters. 3. v ref (see table 24). 4. the minimum limit requirement is for testing purposes. the leakage current on the v ref pin should be minimal. input operating conditions table 24: dc electrical characteristics and input conditions all voltages are referenced to v ss parameter/condition symbol min nom max unit notes v in low; dc/commands/address busses v il v ss n/a see table 25 v v in high; dc/commands/address busses v ih see table 25 n/a v dd v input reference voltage command/address bus v refca(dc) 0.49 v dd 0.5 v dd 0.51 v dd v 1, 2 i/o reference voltage dq bus v refdq(dc) 0.49 v dd 0.5 v dd 0.51 v dd v 2, 3 i/o reference voltage dq bus in self refresh v refdq(sr) v ss 0.5 v dd v dd v4 command/address termination voltage (system level, not direct dram input) v tt C 0.5 v ddq Cv5 notes: 1. v refca(dc) is expected to be approximately 0.5 v dd and to track variations in the dc level. externally generated peak noise (noncommon mode) on v refca may not exceed 1% v dd around the v refca(dc) value. peak-to-peak ac noise on v refca should not ex- ceed 2% of v refca(dc) . 2. dc values are determined to be less than 20 mhz in frequency. dram must meet specifi- cations if the dram induces additional ac noise greater than 20 mhz in frequency. 3. v refdq(dc) is expected to be approximately 0.5 v dd and to track variations in the dc level. externally generated peak noise (noncommon mode) on v refdq may not exceed 1% v dd around the v refdq(dc) value. peak-to-peak ac noise on v refdq should not ex- ceed 2% of v refdq(dc) . 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
4. v refdq(dc) may transition to v refdq(sr) and back to v refdq(dc) when in self refresh, within restrictions outlined in the self refresh section. 5. v tt is not applied directly to the device. v tt is a system supply for signal termination re- sistors. minimum and maximum values are system-dependent. table 25: input switching conditions parameter/condition symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit command and address input high ac voltage: logic 1 @ 175mv v ih(ac175)min 175 175 C mv input high ac voltage: logic 1 @ 150mv v ih(ac150)min 150 150 C mv input high ac voltage: logic 1 @ 135 mv v ih(ac135)min C C 135 mv input high ac voltage: logic 1 @ 125 mv v ih(ac125)min C C 125 mv input high dc voltage: logic 1 @ 100 mv v ih(dc100)min 100 100 100 mv input low dc voltage: logic 0 @ C100mv v il(dc100)max C100 C100 C100 mv input low ac voltage: logic 0 @ C125mv v il(ac125)max C C C125 mv input low ac voltage: logic 0 @ C135mv v il(ac135)max C C C135 mv input low ac voltage: logic 0 @ C150mv v il(ac150)max C150 C150 C mv input low ac voltage: logic 0 @ C175mv v il(ac175)max C175 C175 C mv dq and dm input high ac voltage: logic 1 v ih(ac175)min 175 C C mv input high ac voltage: logic 1 v ih(ac150)min 150 150 C mv input high ac voltage: logic 1 v ih(ac135)min C C 135 mv input high dc voltage: logic 1 v ih(dc100)min 100 100 100 mv input low dc voltage: logic 0 v il(dc100)max C100 C100 C100 mv input low ac voltage: logic 0 v il(ac135)max C C C135 mv input low ac voltage: logic 0 v il(ac150)max C150 C150 C mv input low ac voltage: logic 0 v il(ac175)max C175 C C mv notes: 1. all voltages are referenced to v ref . v ref is v refca for control, command, and address. all slew rates and setup/hold times are specified at the dram ball. v ref is v refdq for dq and dm inputs. 2. input setup timing parameters ( t is and t ds) are referenced at v il(ac) /v ih(ac) , not v ref(dc) . 3. input hold timing parameters ( t ih and t dh) are referenced at v il(dc) /v ih(dc) , not v ref(dc) . 4. single-ended input slew rate = 1 v/ns; maximum input voltage swing under test is 900mv (peak-to-peak). 5. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3-800, two input ac levels are defined: v ih(ac175),min and v ih(ac150),min (corresponding v il(ac175),min and v il(ac150),min ). for ddr3-800, the address/ command inputs must use either v ih(ac175),min with t is(ac175) of 200ps or v ih(ac150),min with t is(ac150) of 350ps; independently, the data inputs must use either v ih(ac175),min with t ds(ac175) of 75ps or v ih(ac150),min with t ds(ac150) of 125ps. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 13: input signal 0.575v 0.0v 0.650v 0.720v 0.735v 0.750v 0.765v 0.780v 0.850v 0.925v v il(ac) v il(dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih(dc) v ih(ac) 1.50v 1.90v C0.40v v ddq v ddq + 0.4v narrow pulse width v ss - 0.4v narrow pulse width v ss 0.575v 0.650v 0.720v 0.735v 0.750v 0.765v 0.780v 0.850v 0.925v minimum v il and v ih levels v ih(dc) v ih(ac) v il(ac) v il(dc) v il and v ih levels with ringback note: 1. numbers in diagrams reflect nominal values. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
ac overshoot/undershoot specification table 26: control and address pins parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 maximum peak amplitude al- lowed for overshoot area (see figure 14) 0.4v 0.4v 0.4v 0.4v 0.4v 0.4v maximum peak amplitude al- lowed for undershoot area (see figure 15) 0.4v 0.4v 0.4v 0.4v 0.4v 0.4v maximum overshoot area above v dd (see figure 14) 0.67 vns 0.5 vns 0.4 vns 0.33 vns 0.28 vns 0.25 vns maximum undershoot area be- low v ss (see figure 15) 0.67 vns 0.5 vns 0.4 vns 0.33 vns 0.28 vns 0.25 vns table 27: clock, data, strobe, and mask pins parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 maximum peak amplitude al- lowed for overshoot area (see figure 14) 0.4v 0.4v 0.4v 0.4v 0.4v 0.4v maximum peak amplitude al- lowed for undershoot area (see figure 15) 0.4v 0.4v 0.4v 0.4v 0.4v 0.4v maximum overshoot area above v dd /v ddq (see figure 14) 0.25 vns 0.19 vns 0.15 vns 0.13 vns 0.11 vns 0.10 vns maximum undershoot area be- low v ss /v ssq (see figure 15) 0.25 vns 0.19 vns 0.15 vns 0.13 vns 0.11 vns 0.10 vns figure 14: overshoot maximum amplitude overshoot area v dd /v ddq time (ns) volts (v) figure 15: ndershoot maximum amplitude undershoot area v ss /v ssq time (ns) volts (v) 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 28: differential input operating conditions (ck, ck# and dqs, dqs#) parameter/condition symbol min max unit notes differential input voltage logic high - slew v ih,diff 200 n/a mv 4 differential input voltage logic low - slew v il,diff n/a C200 mv 4 differential input voltage logic high v ih,diff(ac) 2 (v ih(ac) - v ref )v dd /v ddq mv 5 differential input voltage logic low v il,diff(ac) v ss /v ssq 2 (v il(ac) -v ref )mv 6 differential input crossing voltage relative to v dd /2 for dqs, dqs#; ck, ck# v ix v ref(dc) - 150 v ref(dc) + 150 mv 4, 7 differential input crossing voltage relative to v dd /2 for ck, ck# v ix (175) v ref(dc) - 175 v ref(dc) + 175 mv 4, 7, 8 single-ended high level for strobes v seh v ddq /2 + 175 v ddq mv 5 single-ended high level for ck, ck# v dd /2 + 175 v dd mv 5 single-ended low level for strobes v sel v ssq v ddq /2 - 175 mv 6 single-ended low level for ck, ck# v ss v dd /2 - 175 mv 6 notes: 1. clock is referenced to v dd and v ss . data strobe is referenced to v ddq and v ssq . 2. reference is v refca(dc) for clock and v refdq(dc) for strobe. 3. differential input slew rate = 2 v/ns 4. defines slew rate reference points, relative to input crossing voltages. 5. minimum dc limit is relative to single-ended signals; overshoot specifications are appli- cable. 6. maximum dc limit is relative to single-ended signals; undershoot specifications are ap- plicable. 7. the typical value of v ix(ac) is expected to be about 0.5 v dd of the transmitting device, and v ix(ac) is expected to track variations in v dd . v ix(ac) indicates the voltage at which differential input signals must cross. 8. the v ix extended range (175mv) is allowed only for the clock; this v ix extended range is only allowed when the following conditions are met: the single-ended input signals are monotonic, have the single-ended swing v sel , v seh of at least v dd /2 250mv, and the differential slew rate of ck, ck# is greater than 3 v/ns. 9. v ix must provide 25mv (single-ended) of the voltages separation. 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 16: v ix for differential signals ck, dqs v dd /2, v ddq /2 v dd /2, v ddq /2 v ix v ix ck#, dqs# v dd , v ddq ck, dqs v dd , v ddq v ss , v ssq ck#, dqs# v ss , v ssq x x x x x x x x v ix v ix figure 17: single-ended requirements for differential signals v ss or v ssq v dd or v ddq v sel,max v seh,min v seh v sel ck or dqs v dd /2 or v ddq /2 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 18: definition of differential ac-swing and t dvac v ih,diff(ac)min 0.0 v il,diff,max t dvac v ih,diff,min v il,diff(ac)max half cycle t dvac ck - ck# dqs - dqs# table 29: allowed time before ringback ( t dvac) for ck - ck# and dqs - dqs# slew rate (v/ns) t dvac (ps) at |v ih,diff(ac) to v il,diff(ac) | 350mv 300mv >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 note: 1. below v il(ac) 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
slew rate definitions for single-ended input signals setup ( t is and t ds) nominal slew rate for a rising signal is defined as the slew rate be- tween the last crossing of v ref and the first crossing of v ih(ac)min . setup ( t is and t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref and the first crossing of v il(ac)max . hold ( t ih and t dh) nominal slew rate for a rising signal is defined as the slew rate be- tween the last crossing of v il(dc)max and the first crossing of v ref . hold ( t ih and t dh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref (see figure 19 (page 53)). table 30: single-ended input slew rate definition input slew rates (linear signals) measured calculation input edge from to setup rising v ref v ih(ac)min v ih(ac)min - v ref ? trs se falling v ref v il(ac)max v ref - v il(ac)max ? tfs se hold rising v il(dc)max v ref v ref - v il(dc)max ? tfh se falling v ih(dc)min v ref v ih(dc)min - v ref ? trsh se 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 19: nominal slew rate definition for single-ended input signals ? trs se ? tfs se ? trh se ? tfh se v refdq or v refca v ih(ac)min v ih(dc)min v il(ac)max v il(dc)max v refdq or v refca v ih(ac)min v ih(dc)min v il(ac)max v il(dc)max setup hold single-ended input voltage (dq, cmd, addr) single-ended input voltage (dq, cmd, addr) 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
slew rate definitions for differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and meas- ured, as shown in table 31 and figure 20. the nominal slew rate for a rising signal is defined as the slew rate between v il,diff,max and v ih,diff,min . the nominal slew rate for a falling signal is defined as the slew rate between v ih,diff,min and v il,diff,max . table 31: differential input slew rate definition differential input slew rates (linear signals) measured calculation input edge from to ck and dqs reference rising v il,diff,max v ih,diff,min v ih,diff,min - v il,diff,max ? tr diff falling v ih,diff,min v il,diff,max v ih,diff,min - v il,diff,max ? tf diff figure 20: nominal differential input slew rate definition for dqs, dqs# and ck, ck# ? tr diff ? tf diff v ih,diff,min v il,diff,max 0 differential input voltage (dqs, dqs#; ck, ck#) 2gb: x4, x8, x16 ddr3 sdram electrical specifications C dc and ac pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
output driver impedance the output driver impedance is selected by mr1[5,1] during initialization. the selected value is able to maintain the tight tolerances specified if proper zq calibration is per- formed. output specifications refer to the default output driver unless specifically sta- ted otherwise. a functional representation of the output buffer is shown below. the out- put driver impedance r on is defined by the value of the external reference resistor rzq as follows: ? r on,x = rzq / y (with rzq = 240 r x or 40 with y = 7 or 6, respectively) the individual pull-up and pull-down resistors r on(pu) and r on(pd) are defined as fol- lows: ? r on(pu) = ( v ddq - v out )/| i out |, when r on(pd) is turned off ? r on(pd) = ( v out )/| i out |, when r on(pu) is turned off figure 21: output driver r on(pu) r on(pd) output driver to other circuitry such as rcv, . . . chip in drive mode v ddq v ssq i pu i pd i out v out dq 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
34 ohm output driver impedance the 34 driver (mr1[5, 1] = 01) is the default driver. unless otherwise stated, all timings and specifications listed herein apply to the 34 driver only. its impedance r on is de- fined by the value of the external reference resistor rzq as follows: r on34 = rzq/7 (with nominal rzq = 240 1%) and is actually 34.3 r table 32: 34 ohm driver impedance characteristics mr1[5,1] r on resistor v out min nom max unit notes 0,1 r on34(pd) 0.2/v ddq 0.6 1.0 1.1 rzq/7 0.5/v ddq 0.9 1.0 1.1 rzq/7 0.8/v ddq 0.9 1.0 1.4 rzq/7 r on34(pu) 0.2/v ddq 0.9 1.0 1.4 rzq/7 0.5/v ddq 0.9 1.0 1.1 rzq/7 0.8/v ddq 0.6 1.0 1.1 rzq/7 pull-up/pull-down mismatch (mm pupd ) 0.5/v ddq C10% n/a 10 % 2 notes: 1. tolerance limits assume rzq of 240 1% and are applicable after proper zq calibra- tion has been performed at a stable temperature and voltage: v ddq = v dd ; v ssq = v ss ). refer to 34 ohm output driver sensitivity (page 58) if either the temperature or the voltage changes after calibration. 2. measurement definition for mismatch between pull-up and pull-down (mm pupd ). meas- ure both r on(pu) and r on(pd) at 0.5 v ddq : mm pupd = 100 r on(pu) - r on(pd) r on,nom 3. for it and at (1gb only) devices, the minimum values are derated by 6% when the de- vice operates between C40c and 0c (t c ). 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
34 ohm driver the 34 drivers current range has been calculated and summarized in table 34 (page 57) v dd = 1.5v, table 35 (page 57) for v dd = 1.57v, and table 36 (page 58) for v dd = 1.42v. the individual pull-up and pull-down resistors r on34(pd) and r on34(pu) are defined as follows: ? r on34(pd) = ( v out )/| i out |; r on34(pu) is turned off ? r on34(pu) = ( v ddq - v out )/| i out |; r on34(pd) is turned off table 33: 34 ohm driver pull-up and pull-down impedance calculations r on min nom max unit rzq = 240 r 237.6 240 242.4 rzq/7 = (240 r 33.9 34.3 34.6 mr1[5,1] r on resistor v out min nom max unit 0, 1 r on34(pd) 0.2 v ddq 20.4 34.3 38.1 0.5 v ddq 30.5 34.3 38.1 0.8 v ddq 30.5 34.3 48.5 r on34(pu) 0.2 v ddq 30.5 34.3 48.5 0.5 v ddq 30.5 34.3 38.1 0.8 v ddq 20.4 34.3 38.1 table 34: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.5v mr1[5,1] r on resistor v out max nom min unit 0, 1 r on34(pd) i ol @ 0.2 v ddq 14.7 8.8 7.9 ma i ol @ 0.5 v ddq 24.6 21.9 19.7 ma i ol @ 0.8 v ddq 39.3 35.0 24.8 ma r on34(pu) i oh @ 0.2 v ddq 39.3 35.0 24.8 ma i oh @ 0.5 v ddq 24.6 21.9 19.7 ma i oh @ 0.8 v ddq 14.7 8.8 7.9 ma table 35: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.575v mr1[5,1] r on resistor v out max nom min unit 0, 1 r on34(pd) i ol @ 0.2 v ddq 15.5 9.2 8.3 ma i ol @ 0.5 v ddq 25.8 23 20.7 ma i ol @ 0.8 v ddq 41.2 36.8 26 ma r on34(pu) i oh @ 0.2 v ddq 41.2 36.8 26 ma i oh @ 0.5 v ddq 25.8 23 20.7 ma i oh @ 0.8 v ddq 15.5 9.2 8.3 ma 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 36: 34 ohm driver i oh /i ol characteristics: v dd = v ddq = 1.425v mr1[5,1] r on resistor v out max nom min unit 0, 1 r on34(pd) i ol @ 0.2 v ddq 14.0 8.3 7.5 ma i ol @ 0.5 v ddq 23.3 20.8 18.7 ma i ol @ 0.8 v ddq 37.3 33.3 23.5 ma r on34(pu) i oh @ 0.2 v ddq 37.3 33.3 23.5 ma i oh @ 0.5 v ddq 23.3 20.8 18.7 ma i oh @ 0.8 v ddq 14.0 8.3 7.5 ma 34 ohm output driver sensitivity if either the temperature or the voltage changes after zq calibration, then the tolerance limits listed in table 32 (page 56) can be expected to widen according to table 37 and table 38 (page 58). table 37: 34 ohm output driver sensitivity definition symbol min max unit r on(pd) @ 0.2 v ddq 0.6 - dr on dtl | t| - dr on dvl | v| 1.1 + dr on dtl | t| + dr on dvl | v| rzq/7 r on(pd) @ 0.5 v ddq 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/7 r on(pd) @ 0.8 v ddq 0.9 - dr on dth | t| - dr on dvh | v| 1.4 + dr on dth | t| + dr on dvh | v| rzq/7 r on(pu) @ 0.2 v ddq 0.9 - dr on dtl | t| - dr on dvl | v| 1.4 + dr on dtl | t| + dr on dvl | v| rzq/7 r on(pu) @ 0.5 v ddq 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/7 r on(pu) @ 0.8 v ddq 0.6 - dr on dth | t| - dr on dvh | v| 1.1 + dr on dth | t| + dr on dvh | v| rzq/7 note: 1. t = t - t (@calibration) v = v ddq - v ddq(@calibration) ; and v dd = v ddq . table 38: 34 ohm output driver voltage and temperature sensitivity change min max unit dr on dtm 0 1.5 %/c dr on dvm 0 0.13 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.13 %/mv dr on dth 0 1.5 %/c dr on dvh 0 0.13 %/mv 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
alternative 40 ohm driver table 39: 40 ohm driver impedance characteristics mr1[5,1] r on resistor v out min nom max unit 0,0 r on40(pd) 0.2 v ddq 0.6 1.0 1.1 rzq/6 0.5 v ddq 0.9 1.0 1.1 rzq/6 0.8 v ddq 0.9 1.0 1.4 rzq/6 r on40(pu) 0.2 v ddq 0.9 1.0 1.4 rzq/6 0.5 v ddq 0.9 1.0 1.1 rzq/6 0.8 v ddq 0.6 1.0 1.1 rzq/6 pull-up/pull-down mismatch (mm pupd ) 0.5 v ddq C10% n/a 10 % notes: 1. tolerance limits assume rzq of 240 1% and are applicable after proper zq calibra- tion has been performed at a stable temperature and voltage ( v ddq = v dd ; v ssq = v ss ). refer to 40 ohm output driver sensitivity (page 59) if either the temperature or the voltage changes after calibration. 2. measurement definition for mismatch between pull-up and pull-down (mm pupd ). meas- ure both r on(pu) and r on(pd) at 0.5 v ddq : mm pupd = 100 r on(pu) - r on(pd) r on,nom 3. for it and at (1gb only) devices, the minimum values are derated by 6% when the de- vice operates between C40c and 0c (t c ). 40 ohm output driver sensitivity if either the temperature or the voltage changes after i/o calibration, then the tolerance limits listed in table 39 can be expected to widen according to table 40 and table 41 (page 60). table 40: 40 ohm output driver sensitivity definition symbol min max unit r on(pd) @ 0.2 v ddq 0.6 - dr on dtl | t| - dr on dvl | v| 1.1 + dr on dtl | t| + dr on dvl | v| rzq/6 r on(pd) @ 0.5 v ddq 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/6 r on(pd) @ 0.8 v ddq 0.9 - dr on dth | t| - dr on dvh | v| 1.4 + dr on dth | t| + dr on dvh | v| rzq/6 r on(pu) @ 0.2 v ddq 0.9 - dr on dtl | t| - dr on dvl | v| 1.4 + dr on dtl | t| + dr on dvl | v| rzq/6 r on(pu) @ 0.5 v ddq 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/6 r on(pu) @ 0.8 v ddq 0.6 - dr on dth | t| - dr on dvh | v| 1.1 + dr on dth | t| + dr on dvh | v| rzq/6 note: 1. t = t - t (@calibration) v = v ddq - v ddq(@calibration) ; and v dd = v ddq . 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 41: 40 ohm output driver voltage and temperature sensitivity change min max unit dr on dtm 0 1.5 %/c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.15 %/mv dr on dth 0 1.5 %/c dr on dvh 0 0.15 %/mv 2gb: x4, x8, x16 ddr3 sdram output driver impedance pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
output characteristics and operating conditions the dram uses both single-ended and differential output drivers. the single-ended output driver is summarized below, while the differential output driver is summarized in table 43 (page 62). table 42: single-ended output driver characteristics all voltages are referenced to v ss parameter/condition symbol min max unit notes output leakage current: dq are disabled; 0v v out v ddq ; odt is disabled; odt is high i oz C5 5 a 1 output slew rate: single-ended; for rising and falling edges, measure between v ol(ac) = v ref - 0.1 v ddq and v oh(ac) = v ref + 0.1 v ddq srq se 2.5 6 v/ns 1, 2, 3, 4 single-ended dc high-level output voltage v oh(dc) 0.8 v ddq v 1, 2, 5 single-ended dc mid-point level output voltage v om(dc) 0.5 v ddq v 1, 2, 5 single-ended dc low-level output voltage v ol(dc) 0.2 v ddq v 1, 2, 5 single-ended ac high-level output voltage v oh(ac) v tt + 0.1 v ddq v 1, 2, 3, 6 single-ended ac low-level output voltage v ol(ac) v tt - 0.1 v ddq v 1, 2, 3, 6 delta r on between pull-up and pull-down for dq/dqs mm pupd C10 10 % 1, 7 test load for ac timing and output slew rates output to v tt (v ddq /2) via 25 resistor 3 notes: 1. rzq of 240 1% with rzq/7 enabled (default 34 driver) and is applicable after prop- er zq calibration has been performed at a stable temperature and voltage ( v ddq = v dd ; v ssq = v ss ). 2. v tt = v ddq /2. 3. see figure 24 (page 63) for the test load configuration. 4. the 6 v/ns maximum is applicable for a single dq signal when it is switching either from high to low or low to high while the remaining dq signals in the same byte lane are either all static or all switching in the opposite direction. for all other dq signal switch- ing combinations, the maximum limit of 6 v/ns is reduced to 5 v/ns. 5. see table 32 (page 56) for iv curve linearity. do not use ac test load. 6. see table 44 (page 64) for output slew rate. 7. see table 32 (page 56) for additional information. 8. see figure 22 (page 62) for an example of a single-ended output signal. 2gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 43: differential output driver characteristics all voltages are referenced to v ss parameter/condition symbol min max unit notes output leakage current: dq are disabled; 0v v out v ddq ; odt is disabled; odt is high i oz C5 5 a 1 output slew rate: differential; for rising and falling edges, measure between v ol,diff(ac) = C0.2 v ddq and v oh,diff(ac) = +0.2 v ddq srq diff 5 12 v/ns 1 output differential cross-point voltage v ox(ac) v ref - 150 v ref + 150 mv 1, 2, 3 differential high-level output voltage v oh,diff(ac) +0.2 v ddq v 1, 4 differential low-level output voltage v ol,diff(ac) C0.2 v ddq v 1, 4 delta ron between pull-up and pull-down for dq/dqs mm pupd C10 10 % 1, 5 test load for ac timing and output slew rates output to v tt (v ddq /2) via 25 resistor 3 notes: 1. rzq of 240 1% with rzq/7 enabled (default 34 driver) and is applicable after prop- er zq calibration has been performed at a stable temperature and voltage ( v ddq = v dd ; v ssq = v ss ). 2. v ref = v ddq /2; slew rate @ 5 v/ns, interpolate for faster slew rate. 3. see figure 24 (page 63) for the test load configuration. 4. see table 45 (page 65) for the output slew rate. 5. see table 32 (page 56) for additional information. 6. see figure 23 (page 63) for an example of a differential output signal. figure 22: dq output signal v oh(ac) min output max output v ol(ac) 2gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 23: differential output signal v oh min output max output v ol v ox(ac)max v ox(ac)min x x x x reference output load figure 24 represents the effective reference load of 25 used in defining the relevant de- vice ac timing parameters (except odt reference timing) as well as the output slew rate measurements. it is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. figure 24: reference output load for ac timing and output slew rate timing reference point dq dqs dqs# dut v ref v tt = v ddq /2 v ddq /2 zq rzq = 240 v ss r tt = 25 2gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
slew rate definitions for single-ended output signals the single-ended output driver is summarized in table 42 (page 61). with the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between v ol(ac) and v oh(ac) for single-ended signals. table 44: single-ended output slew rate definition single-ended output slew rates (linear signals) measured calculation output edge from to dq rising v ol(ac) v oh(ac) v oh(ac) - v ol(ac) ? tr se falling v oh(ac) v ol(ac) v oh(ac) - v ol(ac) ? tf se figure 25: nominal slew rate definition for single-ended output signals v oh(ac) v ol(ac) v tt ? tf se ? tr se 2gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
slew rate definitions for differential output signals the differential output driver is summarized in table 43 (page 62). with the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between v ol(ac) and v oh(ac) for differential signals. table 45: differential output slew rate definition differential output slew rates (linear signals) measured calculation output edge from to dqs, dqs# rising v ol,diff(ac) v oh,diff(ac) v oh,diff(ac) - v ol,diff(ac) ? tr diff falling v oh,diff(ac) v ol,diff(ac) v oh,diff(ac) - v ol,diff(ac) ? tf diff figure 26: nominal differential output slew rate definition for dqs, dqs# ? tr diff ? tf diff v oh,diff(ac) v ol,diff(ac) 0 2gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
speed bin tables table 46: ddr3-1066 speed bins ddr3-1066 speed bin -187e -187 unit notes cl- t rcd- t rp 7-7-7 8-8-8 parameter symbol min max min max internal read command to first data t aa 13.125 C 15 C ns activate to internal read or write delay time t rcd 13.125 C 15 C ns precharge command period t rp 13.125 C 15 C ns activate-to-activate or refresh command period t rc 50.625 C 52.5 C ns activate-to-precharge command period t ras 37.5 9 x t refi 37.5 9 x t refi ns 1 cl = 5 cwl = 5 t ck (avg) 3.0 3.3 3.0 3.3 ns 2 cwl = 6 t ck (avg) reserved reserved ns 3 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 ns 2 cwl = 6 t ck (avg) reserved reserved ns 3 cl = 7 cwl = 5 t ck (avg) reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 reserved ns 2, 3 cl = 8 cwl = 5 t ck (avg) reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 ns 2 supported cl settings 5, 6, 7, 8 5, 6, 8 ck supported cwl settings 5, 6 5, 6 ck notes: 1. t refi depends on t oper . 2. the cl and cwl settings result in t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be fulfilled. 3. reserved settings are not allowed. 2gb: x4, x8, x16 ddr3 sdram speed bin tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 47: ddr3-1333 speed bins ddr3-1333 speed bin -15e 1 -15 2 unit notes cl- t rcd- t rp 9-9-9 10-10-10 parameter symbol min max min max internal read command to first data t aa 13.5 C 15 C ns activate to internal read or write delay time t rcd 13.5 C 15 C ns precharge command period t rp 13.5 C 15 C ns activate-to-activate or refresh command period t rc 49.5 C 51 C ns activate-to-precharge command period t ras 36 9 x t refi 36 9 x t refi ns 3 cl = 5 cwl = 5 t ck (avg) 3.0 3.3 3.0 3.3 ns 4 cwl = 6, 7 t ck (avg) reserved reserved ns 5 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 ns 4 cwl = 6 t ck (avg) reserved reserved ns 5 cwl = 7 t ck (avg) reserved reserved ns 5 cl = 7 cwl = 5 t ck (avg) reserved reserved ns 5 cwl = 6 t ck (avg) 1.875 <2.5 reserved ns 4, 5 cwl = 7 t ck (avg) reserved reserved ns 5 cl = 8 cwl = 5 t ck (avg) reserved reserved ns 5 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 ns 4 cwl = 7 t ck (avg) reserved reserved ns 5 cl = 9 cwl = 5, 6 t ck (avg) reserved reserved ns 5 cwl = 7 t ck (avg) 1.5 <1.875 reserved ns 4, 5 cl = 10 cwl = 5, 6 t ck (avg) reserved reserved ns 5 cwl = 7 t ck (avg) 1.5 <1.875 1.5 <1.875 ns 4 supported cl settings 5, 6, 7, 8, 9, 10 5, 6, 8, 10 ck supported cwl settings 5, 6, 7 5, 6, 7 ck notes: 1. the -15e speed grade is backward compatible with 1066, cl = 7 (-187e). 2. the -15 speed grade is backward compatible with 1066, cl = 8 (-187). 3. t refi depends on t oper . 4. the cl and cwl settings result in t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be fulfilled. 5. reserved settings are not allowed. 2gb: x4, x8, x16 ddr3 sdram speed bin tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 48: ddr3-1600 speed bins ddr3-1600 speed bin -125 1 unit notes cl- t rcd- t rp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 C ns activate to internal read or write delay time t rcd 13.75 C ns precharge command period t rp 13.75 C ns activate-to-activate or refresh command period t rc 48.75 C ns activate-to-precharge command period t ras 35 9 x t refi ns 2 cl = 5 cwl = 5 t ck (avg) 3.0 3.3 ns 3 cwl = 6, 7, 8 t ck (avg) reserved ns 4 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 ns 3 cwl = 6 t ck (avg) reserved ns 4 cwl = 7, 8 t ck (avg) reserved ns 4 cl = 7 cwl = 5 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cwl = 7 t ck (avg) reserved ns 4 cwl = 8 t ck (avg) reserved ns 4 cl = 8 cwl = 5 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cwl = 7 t ck (avg) reserved ns 4 cwl = 8 t ck (avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cwl = 8 t ck (avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cwl = 8 t ck (avg) reserved ns 4 cl = 11 cwl = 5, 6, 7 t ck (avg) reserved ns 4 cwl = 8 t ck (avg) 1.25 <1.5 ns 3 supported cl settings 5, 6, 7, 8, 9, 10, 11 ck supported cwl settings 5, 6, 7, 8 ck notes: 1. the -125 speed grade is backward compatible with 1333, cl = 9 (-15e) and 1066, cl = 7 (-187e). 2. t refi depends on t oper . 3. the cl and cwl settings result in t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be fulfilled. 4. reserved settings are not allowed. 2gb: x4, x8, x16 ddr3 sdram speed bin tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 49: ddr3-1866 speed bins ddr3-1866 speed bin -107 1 unit notes cl- t rcd- t rp 13-13-13 parameter symbol min max internal read command to first data t aa 13.91 20 activate to internal read or write delay time t rcd 13.91 C ns precharge command period t rp 13.91 C ns activate-to-activate or refresh command period t rc 48.91 C ns activate-to-precharge command period t ras 34 9 x t refi ns 2 cl = 5 cwl = 5 t ck (avg) 3.0 3.3 ns 3 cwl = 6, 7, 8, 9 t ck (avg) reserved ns 4 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 ns 3 cwl = 6, 7, 8, 9 t ck (avg) reserved ns 4 cl = 7 cwl = 5, 7, 8, 9 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cl = 8 cwl = 5, 8, 9 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cwl = 7 t ck (avg) reserved ns 4 cl = 9 cwl = 5, 6, 8, 9 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cl = 10 cwl = 5, 6, 9 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cwl = 8 t ck (avg) reserved ns 3 cl = 11 cwl = 5, 6, 7 t ck (avg) reserved ns 4 cwl = 8 t ck (avg) 1.25 <1.5 ns 3 cwl = 9 t ck (avg) reserved ns 3 cl = 12 cwl = 5, 6, 7, 8 t ck (avg) reserved ns 4 cwl = 9 t ck (avg) reserved ns 3 cl = 13 cwl = 5, 6, 7, 8 t ck (avg) reserved ns 4 cwl = 9 t ck (avg) 1.071 <1.25 ns 3 supported cl settings 5, 6, 7, 8, 9, 10, 11, 13 ck supported cwl settings 5, 6, 7, 8, 9 ck notes: 1. the -107 speed grade is backward compatible with 1600, cl = 11 (-125) , 1333, cl = 9 (-15e) and 1066, cl = 7 (-187e). 2. t refi depends on t oper . 3. the cl and cwl settings result in t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be fulfilled. 4. reserved settings are not allowed. 2gb: x4, x8, x16 ddr3 sdram speed bin tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 50: ddr3-2133 speed bins ddr3-1866 speed bin -093 1 unit notes cl- t rcd- t rp 14-14-14 parameter symbol min max internal read command to first data t aa 13.13 20 activate to internal read or write delay time t rcd 13.13 C ns precharge command period t rp 13.13 C ns activate-to-activate or refresh command period t rc 46.13 C ns activate-to-precharge command period t ras 33 9 x t refi ns 2 cl = 5 cwl = 5 t ck (avg) 3.0 3.3 ns 3 cwl = 6, 7, 8, 9 t ck (avg) reserved ns 4 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 ns 3 cwl = 6, 7, 8, 9 t ck (avg) reserved ns 4 cl = 7 cwl = 5, 7, 8, 9 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cl = 8 cwl = 5, 8, 9 t ck (avg) reserved ns 4 cwl = 6 t ck (avg) 1.875 <2.5 ns 3 cwl = 7 t ck (avg) reserved ns 4 cl = 9 cwl = 5, 6, 8, 9 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cl = 10 cwl = 5, 6, 9 t ck (avg) reserved ns 4 cwl = 7 t ck (avg) 1.5 <1.875 ns 3 cwl = 8 t ck (avg) reserved ns 3 cl = 11 cwl = 5, 6, 7 t ck (avg) reserved ns 4 cwl = 8 t ck (avg) 1.25 <1.5 ns 3 cwl = 9 t ck (avg) reserved ns 3 cl = 12 cwl = 5, 6, 7, 8 t ck (avg) reserved ns 4 cwl = 9 t ck (avg) reserved ns 3 cl = 13 cwl = 5, 6, 7, 8 t ck (avg) reserved ns 4 cwl = 9 t ck (avg) 1.071 <1.25 ns 3 cl = 14 cwl = 5, 6, 7, 8, 9 t ck (avg) reserved reserved ns 4 cwl = 10 t ck (avg) 0.938 <1.071 ns 3 supported cl settings 5, 6, 7, 8, 9, 10, 11, 13, 14 ck supported cwl settings 5, 6, 7, 8, 9 ck notes: 1. the -093 speed grade is backward compatible with 1866, cl = 13 (-107) , 1600, cl = 11 (-125) , 1333, cl = 9 (-15e) and 1066, cl = 7 (-187e). 2. t refi depends on t oper . 3. the cl and cwl settings result in t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be fulfilled. 4. reserved settings are not allowed. 2gb: x4, x8, x16 ddr3 sdram speed bin tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics and ac operating conditions table 51: electrical characteristics and ac operating conditions notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max clock timing clock period average: dll disable mode t c 85c t ck (dll_dis) 8 7800 8 7800 8 7800 8 7800 ns 9, 42 t c = >85c to 95c 8 3900 8 3900 8 3900 8 3900 ns 42 clock period average: dll enable mode t ck (avg) see speed bin tables (page 66) for t ck range allowed ns 10, 11 high pulse width average t ch (avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ck 12 low pulse width average t cl (avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ck 12 clock period jitter dll locked t jitper C100 100 C90 90 C80 80 C70 70 ps 13 dll locking t jitper,lck C90 90 C80 80 C70 70 C60 60 ps 13 clock absolute period t ck (abs) min = t ck (avg) min + t jitper min; max = t ck (avg) max + t jitper max ps clock absolute high pulse width t ch (abs) 0.43 C 0.43 C 0.43 C 0.43 C t ck (avg) 14 clock absolute low pulse width t cl (abs) 0.43 C 0.43 C 0.43 C 0.43 C t ck (avg) 15 cycle-to-cycle jitter dll locked t jitcc 200 180 160 140 ps 16 dll locking t jitcc,lck 180 160 140 120 ps 16 cumulative error across 2 cycles t err2per C147 147 C132 132 C118 118 C103 103 ps 17 3 cycles t err3per C175 175 C157 157 C140 140 C122 122 ps 17 4 cycles t err4per C194 194 C175 175 C155 155 C136 136 ps 17 5 cycles t err5per C209 209 C188 188 C168 168 C147 147 ps 17 6 cycles t err6per C222 222 C200 200 C177 177 C155 155 ps 17 7 cycles t err7per C232 232 C209 209 C186 186 C163 163 ps 17 8 cycles t err8per C241 241 C217 217 C193 193 C169 169 ps 17 9 cycles t err9per C249 249 C224 224 C200 200 C175 175 ps 17 10 cycles t err10per C257 257 C231 231 C205 205 C180 180 ps 17 11 cycles t err11per C263 263 C237 237 C210 210 C184 184 ps 17 12 cycles t err12per C269 269 C242 242 C215 215 C188 188 ps 17 n = 13, 14 . . . 49, 50 cycles t err n per t err n per min = (1 + 0.68ln[ n ]) t jitper min t err n per max = (1 + 0.68ln[ n ]) t jitper max ps 17 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max dq input timing data setup time to dqs, dqs# base (specification) t ds (ac175) 75 C 25 C C C C C ps 18, 19, 44 v ref @ 1 v/ns 250 C 200 C C C C C ps 19, 20 data setup time to dqs, dqs# base (specification) t ds (ac150) 125 C 75 C 30 C 10 C ps 18, 19, 44 v ref @ 1 v/ns 275 C 250 C 180 C 160 C ps 19, 20 data setup time to dqs, dqs# base (specification) t ds (ac135) CCCCCCCCps 18, 19 v ref @ 1 v/ns CCCCCCCCps 19, 20 data hold time from dqs, dqs# base (specification) t dh (dc100) 150 C 100 C 65 C 45 C ps 18, 19 v ref @ 1 v/ns 250 C 200 C 165 C 145 C ps 19, 20 minimum data pulse width t dipw 600 C 490 C 400 C 360 C ps 41 dq output timing dqs, dqs# to dq skew, per access t dqsq C 200 C 150 C 125 C 100 ps dq output hold time from dqs, dqs# t qh 0.38 C 0.38 C 0.38 C 0.38 C t ck (avg) 21 dq low-z time from ck, ck# t lzdq C800 400 C600 300 C500 250 C450 225 ps 22, 23 dq high-z time from ck, ck# t hzdq C 400 C 300 C 250 C 225 ps 22, 23 dq strobe input timing dqs, dqs# rising to ck, ck# rising t dqss C0.25 0.25 C0.25 0.25 C0.25 0.25 C0.27 0.27 ck 25 dqs, dqs# differential input low pulse width t dqsl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck dqs, dqs# differential input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck dqs, dqs# falling setup to ck, ck# rising t dss 0.2 C 0.2 C 0.2 C 0.18 C ck 25 dqs, dqs# falling hold from ck, ck# rising t dsh 0.2 C 0.2 C 0.2 C 0.18 C ck 25 dqs, dqs# differential write preamble t wpre 0.9 C 0.9 C 0.9 C 0.9 C ck dqs, dqs# differential write postamble t wpst 0.3 C 0.3 C 0.3 C 0.3 C ck dq strobe output timing dqs, dqs# rising to/from rising ck, ck# t dqsck C400 400 C300 300 C255 255 C225 225 ps 23 dqs, dqs# rising to/from rising ck, ck# when dll is disabled t dqsck (dll_dis) 110110110110ns26 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max dqs, dqs# differential output high time t qsh 0.38 C 0.38 C 0.40 C 0.40 C ck 21 dqs, dqs# differential output low time t qsl 0.38 C 0.38 C 0.40 C 0.40 C ck 21 dqs, dqs# low-z time (rl - 1) t lzdqs C800 400 C600 300 C500 250 C450 225 ps 22, 23 dqs, dqs# high-z time (rl + bl/2) t hzdqs C 400 C 300 C 250 C 225 ps 22, 23 dqs, dqs# differential read preamble t rpre 0.9 note 24 0.9 note 24 0.9 note 24 0.9 note 24 ck 23, 24 dqs, dqs# differential read postamble t rpst 0.3 note 27 0.3 note 27 0.3 note 27 0.3 note 27 ck 23, 27 command and address timing dll locking time t dllk 512 C 512 C 512 C 512 C ck 28 ctrl, cmd, addr setup to ck,ck# base (specification) t is (ac175) 200 C 125 C 65 C 45 C ps 29, 30, 44 v ref @ 1 v/ns 375 C 300 C 240 C 220 C ps 20, 30 ctrl, cmd, addr setup to ck,ck# base (specification) t is (ac150) 350 C 275 C 190 C 170 C ps 29, 30, 44 v ref @ 1 v/ns 500 C 425 C 340 C 320 C ps 20, 30 ctrl, cmd, addr hold from ck,ck# base (specification) t ih (dc100) 275 C 200 C 140 C 120 C ps 29, 30 v ref @ 1 v/ns 375 C 300 C 240 C 220 C ps 20, 30 minimum ctrl, cmd, addr pulse width t ipw 900 C 780 C 620 C 560 C ps 41 activate to internal read or write delay t rcd see speed bin tables (page 66) for t rcd ns 31 precharge command period t rp see speed bin tables (page 66) for t rp ns 31 activate-to-precharge command period t ras see speed bin tables (page 66) for t ras ns 31, 32 activate-to-activate command period t rc see speed bin tables (page 66) for t rc ns 31, 43 activate-to-activate minimum command period x4/x8 (1kb page size) t rrd min = greater of 4ck or 10ns min = greater of 4ck or 7.5ns min = greater of 4ck or 6ns min = greater of 4ck or 6ns ck 31 x16 (2kb page size) min = greater of 4ck or 10ns min = greater of 4ck or 7.5ns ck 31 four activate windows x4/x8 (1kb page size) t faw 40 C 37.5 C 30 C 30 C ns 31 x16 (2kb page size) 50 C 50 C 45 C 40 C ns 31 write recovery time t wr min = 15ns; max = n/a ns 31, 32, 33,34 delay from start of internal write transaction to internal read command t wtr min = greater of 4ck or 7.5ns; max = n/a ck 31, 34 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max read-to-precharge time t rtp min = greater of 4ck or 7.5ns; max = n/a ck 31, 32 cas#-to-cas# command delay t ccd min = 4ck; max = n/a ck auto precharge write recovery + precharge time t dal min = wr + t rp/ t ck (avg); max = n/a ck mode register set command cycle time t mrd min = 4ck; max = n/a ck mode register set command update delay t mod min = greater of 12ck or 15ns; max = n/a ck multipurpose register read burst end to mode register set for multipurpose register exit t mprr min = 1ck; max = n/a ck calibration timing zqcl command: long calibration time power-up and re- set operation t zqinit 512 C 512 C 512 C 512 C ck normal operation t zqoper 256 C 256 C 256 C 256 C ck zqcs command: short calibration time t zqcs 64 C 64 C 64 C 64 C ck initialization and reset timing exit reset from cke high to a valid command t xpr min = greater of 5ck or t rfc + 10ns; max = n/a ck begin power supply ramp to power supplies stable t vddpr min = n/a; max = 200 ms reset# low to power supplies stable t rps min = 0; max = 200 ms reset# low to i/o and r tt high-z t ioz min = n/a; max = 20 ns 35 refresh timing refresh-to-activate or refresh command period t rfc C 1gb min = 110; max = 70,200 ns t rfc C 2gb min = 160; max = 70,200 ns t rfc C 4gb min = 260; max = 70,200 ns t rfc C 8gb min = 350; max = 70,200 ns maximum refresh period t c 85c C 64 (1x) ms 36 t c > 85c 32 (2x) ms 36 maximum average periodic refresh t c 85c t refi 7.8 (64ms/8192) s 36 t c > 85c 3.9 (32ms/8192) s 36 self refresh timing 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max exit self refresh to commands not requiring a locked dll t xs min = greater of 5ck or t rfc + 10ns; max = n/a ck exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min); max = n/a ck 28 minimum cke low pulse width for self re- fresh entry to self refresh exit timing t ckesr min = t cke (min) + ck; max = n/a ck valid clocks after self refresh entry or power- down entry t cksre min = greater of 5ck or 10ns; max = n/a ck valid clocks before self refresh exit, power-down exit, or reset exit t cksrx min = greater of 5ck or 10ns; max = n/a ck power-down timing cke min pulse width t cke (min) greater of 3ck or 7.5ns greater of 3ck or 5.625ns greater of 3ck or 5.625ns greater of 3ck or 5ns ck command pass disable delay t cpded min = 1; max = n/a ck power-down entry to power-down exit tim- ing t pd min = t cke (min); max = 9 * trefi ck begin power-down period prior to cke registered high t anpd wl - 1ck ck power-down entry period: odt either synchronous or asynchronous pde greater of t anpd or t rfc - refresh command to cke low time ck power-down exit period: odt either synchronous or asynchronous pdx t anpd + t xpdll ck power-down entry minimum timing activate command to power-down entry t actpden min = 1 ck precharge/precharge all command to power-down entry t prpden min = 1 ck refresh command to power-down entry t refpden min = 1 ck 37 mrs command to power-down entry t mrspden min = t mod (min) ck read/read with auto precharge command to power-down entry t rdpden min = rl + 4 + 1 ck write command to power-down entry bl8 (otf, mrs) bc4otf t wrpden min = wl + 4 + t wr/ t ck (avg) ck bc4mrs t wrpden min = wl + 2 + t wr/ t ck (avg) ck 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max write with auto precharge command to power-down entry bl8 (otf, mrs) bc4otf t wrap- den min = wl + 4 + wr + 1 ck bc4mrs t wrap- den min = wl + 2 + wr + 1 ck power-down exit timing dll on, any valid command, or dll off to commands not requiring locked dll t xp min = greater of 3ck or 7.5ns; max = n/a min = greater of 3ck or 6ns; max = n/a ck precharge power-down with dll off to commands requiring a locked dll t xpdll min = greater of 10ck or 24ns; max = n/a ck 28 odt timing r tt synchronous turn-on delay odtlon cwl + al - 2ck ck 38 r tt synchronous turn-off delay odtloff cwl + al - 2ck ck 40 r tt turn-on from odtl on reference t aon C400 400 C300 300 C250 250 C225 225 ps 23, 38 r tt turn-off from odtl off reference t aof 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 ck 39, 40 asynchronous r tt turn-on delay (power-down with dll off) t aonpd min = 2; max = 8.5 ns 38 asynchronous r tt turn-off delay (power-down with dll off) t aofpd min = 2; max = 8.5 ns 40 odt high time with write command and bl8 odth8 min = 6; max = n/a ck odt high time without write command or with write command and bc4 odth4 min = 4; max = n/a ck dynamic odt timing r tt,nom -to-r tt(wr) change skew odtlcnw wl - 2ck ck r tt(wr) -to-r tt,nom change skew - bc4 odtlcwn4 4ck + odtloff ck r tt(wr) -to-r tt,nom change skew - bl8 odtlcwn8 6ck + odtloff ck r tt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 ck 39 write leveling timing first dqs, dqs# rising edge t wlmrd 40 C 40 C 40 C 40 C ck dqs, dqs# delay t wldqsen 25 C 25 C 25 C 25 C ck write leveling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 325 C 245 C 195 C 165 C ps 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 51: electrical characteristics and ac operating conditions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit notes min max min max min max min max write leveling hold from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 325 C 245 C 195 C 165 C ps write leveling output delay t wlo09090907.5ns write leveling output error t wloe 02020202ns 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
notes: 1. ac timing parameters are valid from specified t c min to t c max values. 2. all voltages are referenced to v ss . 3. output timings are only valid for r on34 output buffer selection. 4. the unit t ck (avg) represents the actual t ck (avg) of the input clock under operation. the unit ck represents one clock cycle of the input clock, counting the actual clock edges. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 900mv in the test environ- ment, but input timing is still referenced to v ref (except t is, t ih, t ds, and t dh use the ac/dc trip points and ck, ck# and dqs, dqs# use their crossing points). the minimum slew rate for the input signals used to test the device is 1 v/ns for single-ended inputs and 2 v/ns for differential inputs in the range between v il(ac) and v ih(ac) . 6. all timings that use time-based values (ns, s, ms) should use t ck (avg) to determine the correct number of clocks (table 51 (page 71) uses ck or t ck [avg] interchangeably). in the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. strobe or dqs diff refers to the dqs and dqs# differential crossing point when dqs is the rising edge. clock or ck refers to the ck and ck# differential crossing point when ck is the rising edge. 8. this output load is used for all ac timing (except odt reference timing) and slew rates. the actual test load may be different. the output signal voltage reference point is v ddq /2 for single-ended signals and the crossing point for differential signals (see fig- ure 24 (page 63)). 9. when operating in dll disable mode, micron does not warrant compliance with normal mode timings or functionality. 10. the clocks t ck (avg) is the average clock over any 200 consecutive clocks and t ck (avg) min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 11. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20C60 khz with an additional 1% of t ck (avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below t ck (avg) min. 12. the clocks t ch (avg) and t cl (avg) are the average half clock period over any 200 con- secutive clocks and is the smallest clock half period allowed, with the exception of a de- viation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 13. the period jitter ( t jitper) is the maximum deviation in the clock period from the average or nominal clock. it is allowed in either the positive or negative direction. 14. t ch (abs) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. t cl (abs) is the absolute instantaneous clock low pulse width as measured from one fall- ing edge to the following rising edge. 16. the cycle-to-cycle jitter t jitcc is the amount the clock period can deviate from one cycle to the next. it is important to keep cycle-to-cycle jitter at a minimum during the dll locking time. 17. the cumulative jitter error t errnper, where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. t ds (base) and t dh (base) values are for a single-ended 1 v/ns slew rate dqs and 2 v/ns slew rate differential dqs, dqs#. 19. these parameters are measured from a data signal (dm, dq0, dq1, and so forth) transi- tion edge to its respective data strobe signal (dqs, dqs#) crossing. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
20. the setup and hold times are listed converting the base specification values (to which derating tables apply) to v ref when the slew rate is 1 v/ns. these values, with a slew rate of 1 v/ns, are for reference only. 21. when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jitper (larger of t jitper (min) or t jitper (max) of the input clock (output deratings are relative to the sdram input clock). 22. single-ended signal parameter. 23. the dram output timing is aligned to the nominal or average clock. most output pa- rameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. this results in each parameter becoming larger. the fol- lowing parameters are required to be derated by subtracting t err10per (max): t dqsck (min), t lzdqs (min), t lzdq (min), and t aon (min). the following parameters are re- quired to be derated by subtracting t err10per (min): t dqsck (max), t hz (max), t lzdqs (max), t lzdq max, and t aon (max). the parameter t rpre (min) is derated by subtract- ing t jitper (max), while t rpre (max) is derated by subtracting t jitper (min). 24. the maximum preamble is bound by t lzdqs (max). 25. these parameters are measured from a data strobe signal (dqs, dqs#) crossing to its re- spective clock signal (ck, ck#) crossing. the specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. these parameters should be met whether clock jitter is present. 26. the t dqsck (dll_dis) parameter begins cl + al - 1 cycles after the read command. 27. the maximum postamble is bound by t hzdqs (max). 28. commands requiring a locked dll are: read (and rdap) and synchronous odt com- mands. in addition, after any change of latency t xpdll, timing must be met. 29. t is (base) and t ih (base) values are for a single-ended 1 v/ns control/command/address slew rate and 2 v/ns ck, ck# differential slew rate. 30. these parameters are measured from a command/address signal transition edge to its respective clock (ck, ck#) signal crossing. the specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. these parameters should be met whether clock jitter is present. 31. for these parameters, the ddr3 sdram device supports t n param ( n ck) = ru( t param [ns]/ t ck[avg] [ns]), assuming all input clock jitter specifications are satisfied. for exam- ple, the device will support t n rp ( n ck) = ru( t rp/ t ck[avg]) if all input clock jitter specifi- cations are met. this means that for ddr3-800 6-6-6, of which t rp = 5ns, the device will support t n rp = ru( t rp/ t ck[avg]) = 6 as long as the input clock jitter specifications are met. that is, the precharge command at t0 and the activate command at t0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. during reads and writes with auto precharge, the ddr3 sdram will hold off the in- ternal precharge command until t ras (min) has been satisfied. 33. when operating in dll disable mode, the greater of 4ck or 15ns is satisfied for t wr. 34. the start of the write recovery time is defined as follows: ? for bl8 (fixed by mrs or otf): rising clock edge four clock cycles after wl ? for bc4 (otf): rising clock edge four clock cycles after wl ? for bc4 (fixed by mrs): rising clock edge two clock cycles after wl 35. reset# should be low as soon as power starts to ramp to ensure the outputs are in high-z. until reset# is low, the outputs are at risk of driving and could result in exces- sive current, depending on bus activity. 36. the refresh period is 64ms when t c is less than or equal to 85c. this equates to an aver- age refresh rate of 7.8125s. however, nine refresh commands should be asserted at least once every 70.3s. when t c is greater than 85c, the refresh period is 32ms. 37. although cke is allowed to be registered low after a refresh command when 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
t refpden (min) is satisfied, there are cases where additional time such as t xpdll (min) is required. 38. odt turn-on time min is when the device leaves high-z and odt resistance begins to turn on. odt turn-on time maximum is when the odt resistance is fully on. the odt reference load is shown in on page . designs that were created prior to jedec tighten- ing the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum. 39. half-clock output parameters must be derated by the actual t err10per and t jitdty when input clock jitter is present. this results in each parameter becoming larger. the parame- ters t adc (min) and t aof (min) are each required to be derated by subtracting both t err10per (max) and t jitdty (max). the parameters t adc (max) and t aof (max) are required to be derated by subtracting both t err10per (max) and t jitdty (max). 40. odt turn-off time minimum is when the device starts to turn off odt resistance. odt turn-off time maximum is when the dram buffer is in high-z. the odt reference load is shown in on page . this output load is used for odt timings (see figure 24 (page 63)). 41. pulse width of a input signal is defined as the width between the first crossing of v ref(dc) and the consecutive crossing of v ref(dc) . 42. should the clock rate be larger than t rfc (min), an auto refresh command should have at least one nop command between it and another auto refresh command. ad- ditionally, if the clock rate is slower than 40ns (25 mhz), all refresh commands should be followed by a precharge all command. 43. dram devices should be evenly addressed when being accessed. disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime. 44. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3-800, two input ac levels are defined: v ih(ac175),min and v ih(ac150),min (corresponding v il(ac175),min and v il(ac150),min ). for ddr3-800, the address/ command inputs must use either v ih(ac175),min with t is(ac175) of 200ps or v ih(ac150),min with t is(ac150) of 350ps; independently, the data inputs must use either v ih(ac175),min with t ds(ac175) of 75ps or v ih(ac150),min with t ds(ac150) of 125ps. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics and ac operating conditions table 52: electrical characteristics and ac operating conditions for speed extensions notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max clock timing clock period average: dll disable mode t c = 0c to 85c t ck (dll_dis) 8 7800 8 7800 ns 9, 42 t c = >85c to 95c 8 3900 8 3900 ns 42 clock period average: dll enable mode t ck (avg) see speed bin tables (page 66) for t ck range allowed ns 10, 11 high pulse width average t ch (avg) 0.47 0.53 0.47 0.53 ck 12 low pulse width average t cl (avg) 0.47 0.53 0.47 0.53 ck 12 clock period jitter dll locked t jitper C60 60 C50 50 ps 13 dll locking t jitper,lck C50 50 C40 40 ps 13 clock absolute period t ck (abs) min = t ck (avg) min + t jitper min; max = t ck (avg) max + t jitper max ps clock absolute high pulse width t ch (abs) 0.43 C 0.43 C t ck (avg) 14 clock absolute low pulse width t cl (abs) 0.43 C 0.43 C t ck (avg) 15 cycle-to-cycle jitter dll locked t jitcc 120 120 ps 16 dll locking t jitcc,lck 100 100 ps 16 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max cumulative error across 2 cycles t err2per C88 88 -74 74 ps 17 3 cycles t err3per C105 105 -87 87 ps 17 4 cycles t err4per C117 117 -97 97 ps 17 5 cycles t err5per C126 126 -105 105 ps 17 6 cycles t err6per C133 133 -111 111 ps 17 7 cycles t err7per C139 139 -116 116 ps 17 8 cycles t err8per C145 145 -121 121 ps 17 9 cycles t err9per C150 150 -125 125 ps 17 10 cycles t err10per C154 154 -128 128 ps 17 11 cycles t err11per C158 158 -132 132 ps 17 12 cycles t err12per C161 161 -134 134 ps 17 n = 13, 14 . . . 49, 50 cycles t err n per t err n per min = (1 + 0.68ln[ n ]) t jitper min t err n per max = (1 + 0.68ln[ n ]) t jitper max ps 17 dq input timing data setup time to dqs, dqs# base (specification) @ 2 v/ns t ds (ac135) 68 C 53 C ps 18, 19 v ref @ 2 v/ns 135 C 120.5 C ps 19, 20 data hold time from dqs, dqs# base (specification) @ 2 v/ns t dh (dc100) 70 C 55 C ps 18, 19 v ref @ 2 v/ns 120 C 105 C ps 19, 20 minimum data pulse width t dipw 320 C 280 C ps 41 dq output timing dqs, dqs# to dq skew, per access t dqsq C 85 C 75 ps dq output hold time from dqs, dqs# t qh 0.38 C 0.38 C t ck (avg) 21 dq low-z time from ck, ck# t lzdq C390 195 C360 180 ps 22, 23 dq high-z time from ck, ck# t hzdq C 195 C 180 ps 22, 23 dq strobe input timing dqs, dqs# rising to ck, ck# rising t dqss C0.27 0.27 C0.27 0.27 ck 25 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max dqs, dqs# differential input low pulse width t dqsl 0.45 0.55 0.45 0.55 ck dqs, dqs# differential input high pulse width t dqsh 0.45 0.55 0.45 0.55 ck dqs, dqs# falling setup to ck, ck# rising t dss 0.18 C 0.18 C ck 25 dqs, dqs# falling hold from ck, ck# rising t dsh 0.18 C 0.18 C ck 25 dqs, dqs# differential write preamble t wpre 0.9 C 0.9 C ck dqs, dqs# differential write postamble t wpst 0.3 C 0.3 C ck dq strobe output timing dqs, dqs# rising to/from rising ck, ck# t dqsck C195 195 C180 180 ps 23 dqs, dqs# rising to/from rising ck, ck# when dll is disabled t dqsck (dll_dis) 1 10 1 10 ns 26 dqs, dqs# differential output high time t qsh 0.40 C 0.40 C ck 21 dqs, dqs# differential output low time t qsl 0.40 C 0.40 C ck 21 dqs, dqs# low-z time (rl - 1) t lzdqs C390 195 C360 180 ps 22, 23 dqs, dqs# high-z time (rl + bl/2) t hzdqs C 195 C 180 ps 22, 23 dqs, dqs# differential read preamble t rpre 0.9 note 24 0.9 note 24 ck 23, 24 dqs, dqs# differential read postamble t rpst 0.3 note 27 0.3 note 27 ck 23, 27 command and address timing dll locking time t dllk 512 C 512 C ck 28 ctrl, cmd, addr setup to ck,ck# base (specification) t is (ac135) 65 C 60 C ps 29, 30, 44 v ref @ 1 v/ns 200 C 195 C ps 20, 30 ctrl, cmd, addr setup to ck,ck# base (specification) t is (ac125) 150 C 135 C ps 29, 30, 44 v ref @ 1 v/ns 275 C 260 C ps 20, 30 ctrl, cmd, addr hold from ck,ck# base (specification) t ih (dc100) 100 C 95 C ps 29, 30 v ref @ 1 v/ns 200 C 195 C ps 20, 30 minimum ctrl, cmd, addr pulse width t ipw 535 C 470 C ps 41 activate to internal read or write delay t rcd see speed bin tables (page 66) for t rcd ns 31 precharge command period t rp see speed bin tables (page 66) for t rp ns 31 activate-to-precharge command period t ras see speed bin tables (page 66) for t ras ns 31, 32 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max activate-to-activate command period t rc see speed bin tables (page 66) for t rc ns 31, 43 activate-to-activate minimum command pe- riod 1kb page size t rrd min = greater of 4ck or 5ns ck 31 2kb page size min = greater of 4ck or 6ns ck 31 four activate windows 1kb page size t faw 27 C 25 C ns 31 2kb page size 35 C 35 C ns 31 write recovery time t wr min = 15ns; max = n/a ns 31, 32, 33 delay from start of internal write transac- tion to internal read command t wtr min = greater of 4ck or 7.5ns; max = n/a ck 31, 34 read-to-precharge time t rtp min = greater of 4ck or 7.5ns; max = n/a ck 31, 32 cas#-to-cas# command delay t ccd min = 4ck; max = n/a ck auto precharge write recovery + precharge time t dal min = wr + t rp/ t ck (avg); max = n/a ck mode register set command cycle time t mrd min = 4ck; max = n/a ck mode register set command update delay t mod min = greater of 12ck or 15ns; max = n/a ck multipurpose register read burst end to mode register set for multipurpose register exit t mprr min = 1ck; max = n/a ck calibration timing zqcl command: long calibration time power-up and re- set operation t zqinit min = n/a max = max(512nck, 640ns) ck normal operation t zqoper min = n/a max = max(256nck, 320ns) ck zqcs command: short calibration time min = n/a max = max(64nck, 80ns) t zqcs ck initialization and reset timing exit reset from cke high to a valid command t xpr min = greater of 5ck or t rfc + 10ns; max = n/a ck begin power supply ramp to power supplies stable t vddpr min = n/a; max = 200 ms reset# low to power supplies stable t rps min = 0; max = 200 ms reset# low to i/o and r tt high-z t ioz min = n/a; max = 20 ns 35 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max refresh timing refresh-to-activate or refresh command period t rfc C 1gb min = 110; max = 70,200 ns t rfc C 2gb min = 160; max = 70,200 ns t rfc C 4gb min = 260; max = 70,200 ns t rfc C 8gb min = 350; max = 70,200 ns maximum refresh period t c 85c C 64 (1x) ms 36 t c > 85c 32 (2x) ms 36 maximum average periodic refresh t c 85c t refi 7.8 (64ms/8192) s 36 t c > 85c 3.9 (32ms/8192) s 36 self refresh timing exit self refresh to commands not requiring a locked dll t xs min = greater of 5ck or t rfc + 10ns; max = n/a ck exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min); max = n/a ck 28 minimum cke low pulse width for self re- fresh entry to self refresh exit timing t ckesr min = t cke (min) + ck; max = n/a ck valid clocks after self refresh entry or power- down entry t cksre min = greater of 5ck or 10ns; max = n/a ck valid clocks before self refresh exit, power-down exit, or reset exit t cksrx min = greater of 5ck or 10ns; max = n/a ck power-down timing cke min pulse width t cke (min) greater of 3ck or 5ns ck command pass disable delay t cpded min = 2; max = n/a ck power-down entry to power-down exit tim- ing t pd min = t cke (min); max = 9 * trefi ck begin power-down period prior to cke registered high t anpd wl - 1ck ck power-down entry period: odt either synchronous or asynchronous pde greater of t anpd or t rfc - refresh command to cke low time ck power-down exit period: odt either synchronous or asynchronous pdx t anpd + t xpdll ck 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max power-down entry minimum timing activate command to power-down entry t actpden min = 2 ck precharge/precharge all command to power-down entry t prpden min = 2 ck refresh command to power-down entry t refpden min = 2 ck 37 mrs command to power-down entry t mrspden min = t mod (min) ck read/read with auto precharge command to power-down entry t rdpden min = rl + 4 + 1 ck write command to power-down entry bl8 (otf, mrs) bc4otf t wrpden min = wl + 4 + t wr/ t ck (avg) ck bc4mrs t wrpden min = wl + 2 + t wr/ t ck (avg) ck write with auto pre- charge command to power-down entry bl8 (otf, mrs) bc4otf t wrap- den min = wl + 4 + wr + 1 ck bc4mrs t wrap- den min = wl + 2 + wr + 1 ck power-down exit timing dll on, any valid command, or dll off to commands not requiring locked dll t xp min = greater of 3ck or 6ns; max = n/a ck precharge power-down with dll off to commands requiring a locked dll t xpdll min = greater of 10ck or 24ns; max = n/a ck 28 odt timing r tt synchronous turn-on delay odtl on cwl + al - 2ck ck 38 r tt synchronous turn-off delay odtl off cwl + al - 2ck ck 40 r tt turn-on from odtl on reference t aon C195 195 C180 180 ps 23, 38 r tt turn-off from odtl off reference t aof 0.3 0.7 0.3 0.7 ck 39, 40 asynchronous r tt turn-on delay (power-down with dll off) t aonpd min = 2; max = 8.5 ns 38 asynchronous r tt turn-off delay (power-down with dll off) t aofpd min = 2; max = 8.5 ns 40 odt high time with write command and bl8 odth8 min = 6; max = n/a ck 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 52: electrical characteristics and ac operating conditions for speed extensions (continued) notes 1C8 apply to the entire table parameter symbol ddr3-1866 ddr3-2133 unit notes min max min max odt high time without write command or with write command and bc4 odth4 min = 4; max = n/a ck dynamic odt timing r tt,nom -to-r tt(wr) change skew odtlcnw wl - 2ck ck r tt(wr) -to-r tt,nom change skew - bc4 odtlcwn4 4ck + odtloff ck r tt(wr) -to-r tt,nom change skew - bl8 odtlcwn8 6ck + odtloff ck r tt dynamic change skew t adc 0.3 0.7 0.3 0.7 ck 39 write leveling timing first dqs, dqs# rising edge t wlmrd 40 C 40 C ck dqs, dqs# delay t wldqsen 25 C 25 C ck write leveling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 140 C 125 C ps write leveling hold from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 140 C 125 C ps write leveling output delay t wlo 0 7.5 0 7 ns write leveling output error t wloe 0 2 0 2 ns 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
notes: 1. ac timing parameters are valid from specified t c min to t c max values. 2. all voltages are referenced to v ss . 3. output timings are only valid for r on34 output buffer selection. 4. the unit t ck (avg) represents the actual t ck (avg) of the input clock under operation. the unit ck represents one clock cycle of the input clock, counting the actual clock edges. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 900mv in the test environ- ment, but input timing is still referenced to v ref (except t is, t ih, t ds, and t dh use the ac/dc trip points and ck, ck# and dqs, dqs# use their crossing points). the minimum slew rate for the input signals used to test the device is 1 v/ns for single-ended inputs (dqs are at 2v/ns for ddr3-1866 and ddr3-2133) and 2 v/ns for differential inputs in the range between v il(ac) and v ih(ac) . 6. all timings that use time-based values (ns, s, ms) should use t ck (avg) to determine the correct number of clocks (table 52 (page 81) uses ck or t ck [avg] interchangeably). in the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. strobe or dqsdiff refers to the dqs and dqs# differential crossing point when dqs is the rising edge. clock or ck refers to the ck and ck# differential crossing point when ck is the rising edge. 8. this output load is used for all ac timing (except odt reference timing) and slew rates. the actual test load may be different. the output signal voltage reference point is v ddq /2 for single-ended signals and the crossing point for differential signals (see fig- ure 24 (page 63)). 9. when operating in dll disable mode, micron does not warrant compliance with normal mode timings or functionality. 10. the clocks t ck (avg) is the average clock over any 200 consecutive clocks and t ck (avg) min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 11. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20C60 khz with an additional 1% of t ck (avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below t ck (avg) min. 12. the clocks t ch (avg) and t cl (avg) are the average half clock period over any 200 con- secutive clocks and is the smallest clock half period allowed, with the exception of a de- viation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 13. the period jitter ( t jitper) is the maximum deviation in the clock period from the average or nominal clock. it is allowed in either the positive or negative direction. 14. t ch (abs) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. t cl (abs) is the absolute instantaneous clock low pulse width as measured from one fall- ing edge to the following rising edge. 16. the cycle-to-cycle jitter t jitcc is the amount the clock period can deviate from one cycle to the next. it is important to keep cycle-to-cycle jitter at a minimum during the dll locking time. 17. the cumulative jitter error t errnper, where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. t ds (base) and t dh (base) values are for a single-ended 1 v/ns slew rate dqs (dqs are at 2v/ns for ddr3-1866 and ddr3-2133) and 2 v/ns slew rate differential dqs, dqs#. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
19. these parameters are measured from a data signal (dm, dq0, dq1, and so forth) transi- tion edge to its respective data strobe signal (dqs, dqs#) crossing. 20. the setup and hold times are listed converting the base specification values (to which derating tables apply) to v ref when the slew rate is 1 v/ns (dqs are at 2v/ns for ddr3-1866 and ddr3-2133). these values, with a slew rate of 1 v/ns (dqs are at 2v/ns for ddr3-1866 and ddr3-2133), are for reference only. 21. when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jitper (larger of t jitper (min) or t jitper (max) of the input clock (output deratings are relative to the sdram input clock). 22. single-ended signal parameter. 23. the dram output timing is aligned to the nominal or average clock. most output pa- rameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. this results in each parameter becoming larger. the fol- lowing parameters are required to be derated by subtracting t err10per (max): t dqsck (min), t lzdqs (min), t lzdq (min), and t aon (min). the following parameters are re- quired to be derated by subtracting t err10per (min): t dqsck (max), t hz (max), t lzdqs (max), t lzdq (max), and t aon (max). the parameter t rpre (min) is derated by sub- tracting t jitper (max), while t rpre (max) is derated by subtracting t jitper (min). 24. the maximum preamble is bound by t lzdqs (max). 25. these parameters are measured from a data strobe signal (dqs, dqs#) crossing to its re- spective clock signal (ck, ck#) crossing. the specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. these parameters should be met whether clock jitter is present. 26. the t dqsck (dll_dis) parameter begins cl + al - 1 cycles after the read command. 27. the maximum postamble is bound by t hzdqs (max). 28. commands requiring a locked dll are: read (and rdap) and synchronous odt com- mands. in addition, after any change of latency t xpdll, timing must be met. 29. t is (base) and t ih (base) values are for a single-ended 1 v/ns control/command/address slew rate and 2 v/ns ck, ck# differential slew rate. 30. these parameters are measured from a command/address signal transition edge to its respective clock (ck, ck#) signal crossing. the specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. these parameters should be met whether clock jitter is present. 31. for these parameters, the ddr3 sdram device supports t n param ( n ck) = ru( t param [ns]/ t ck[avg] [ns]), assuming all input clock jitter specifications are satisfied. for exam- ple, the device will support t n rp ( n ck) = ru( t rp/ t ck[avg]) if all input clock jitter specifi- cations are met. this means that for ddr3-800 6-6-6, of which t rp = 5ns, the device will support t n rp = ru( t rp/ t ck[avg]) = 6 as long as the input clock jitter specifications are met. that is, the precharge command at t0 and the activate command at t0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. during reads and writes with auto precharge, the ddr3 sdram will hold off the in- ternal precharge command until t ras (min) has been satisfied. 33. when operating in dll disable mode, the greater of 4ck or 15ns is satisfied for t wr. 34. the start of the write recovery time is defined as follows: ? for bl8 (fixed by mrs or otf): rising clock edge four clock cycles after wl ? for bc4 (otf): rising clock edge four clock cycles after wl ? for bc4 (fixed by mrs): rising clock edge two clock cycles after wl 35. reset# should be low as soon as power starts to ramp to ensure the outputs are in high-z. until reset# is low, the outputs are at risk of driving and could result in exces- sive current, depending on bus activity. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
36. the refresh period is 64ms when t c is less than or equal to 85c. this equates to an aver- age refresh rate of 7.8125s. however, nine refresh commands should be asserted at least once every 70.3s. when t c is greater than 85c, the refresh period is 32ms. 37. although cke is allowed to be registered low after a refresh command when t refpden (min) is satisfied, there are cases where additional time such as t xpdll (min) is required. 38. odt turn-on time min is when the device leaves high-z and odt resistance begins to turn on. odt turn-on time maximum is when the odt resistance is fully on. the odt reference load is shown in on page . designs that were created prior to jedec tighten- ing the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum. 39. half-clock output parameters must be derated by the actual t err10per and t jitdty when input clock jitter is present. this results in each parameter becoming larger. the parame- ters t adc (min) and t aof (min) are each required to be derated by subtracting both t err10per (max) and t jitdty (max). the parameters t adc (max) and t aof (max) are required to be derated by subtracting both t err10per (max) and t jitdty (max). 40. odt turn-off time minimum is when the device starts to turn off odt resistance. odt turn-off time maximum is when the dram buffer is in high-z. the odt reference load is shown in on page . this output load is used for odt timings (see figure 24 (page 63)). 41. pulse width of a input signal is defined as the width between the first crossing of v ref(dc) and the consecutive crossing of v ref(dc) . 42. should the clock rate be larger than t rfc (min), an auto refresh command should have at least one nop command between it and another auto refresh command. ad- ditionally, if the clock rate is slower than 40ns (25 mhz), all refresh commands should be followed by a precharge all command. 43. dram devices should be evenly addressed when being accessed. disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime. 44. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3-800, two input ac levels are defined: v ih(ac175),min and v ih(ac150),min (corresponding v il(ac175),min and v il(ac150),min ). for ddr3-800, the address/ command inputs must use either v ih(ac175),min with t is(ac175) of 200ps or v ih(ac150),min with t is(ac150) of 350ps; independently, the data inputs must use either v ih(ac175),min with t ds(ac175) of 75ps or v ih(ac150),min with t ds(ac150) of 125ps. 2gb: x4, x8, x16 ddr3 sdram electrical characteristics and ac operating conditions pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
command and address setup, hold, and derating the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) values (see table 53; values come from table 51 (page 71)) to the t is and t ih derating values (see table 54 (page 92) and table 55 (page 92)), respectively. example: t is (total setup time) = t is (base) + t is. for a valid transition, the input signal has to remain above/below v ih(ac) /v il(ac) for some time t vac (see table 55 (page 92)). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih(ac) /v il(ac) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih(ac) /v il(ac) (see figure 13 (page 47) for input signal requirements). for slew rates that fall between the values listed in table 55 (page 92) and table 58 (page 94), the derat- ing values may be obtained by linear interpolation. setup ( t is) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup ( t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) -to-ac region, use the nominal slew rate for derat- ing value (see figure 27 (page 95)). if the actual signal is later than the nominal slew rate line anywhere between the shaded v ref(dc) -to-ac region, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 29 (page 97)). hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc-to-v ref(dc) region, use the nominal slew rate for derat- ing value (see figure 28 (page 96)). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded dc-to-v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to the v ref(dc) level is used for derating value (see figure 30 (page 98)). table 53: command and address setup and hold values referenced C ac/dc-based symbol 800 1066 1333 1600 1866 2133 unit reference t is(base, ac175) 200 125 65 45 C C ps v ih(ac) /v il(ac) t is(base, ac150) 350 275 190 170 C C ps v ih(ac) /v il(ac) t is(base, ac135) C C C C 65 60 ps v ih(ac) /v il(ac) t is(base, ac125) C C C C 150 135 ps v ih(ac) /v il(ac) t ih(base, dc100) 275 200 140 120 100 95 ps v ih(dc) /v il(dc) 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 54: derating values for t is/ t ih C ac175/dc100-based t is, 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 C2 C4 C2 C4 C2 C4 6 4 14 12 22 20 30 30 38 46 0.8 C6 C10 C6 C10 C6 C10 2 C2 10 6 18 14 26 24 34 40 0.7 C11 C16 C11 C16 C11 C16 C3 C8 5 0 13 8 21 18 29 34 0.6 C17 C26 C17 C26 C17 C26 C9 C18 C1 C10 7 C2 15 8 23 24 0.5 C35 C40 C35 C40 C35 C40 C27 C32 C19 C24 C11 C16 C2 C6 5 10 0.4 C62 C60 C62 C60 C62 C60 C54 C52 C46 C44 C38 C36 C30 C26 C22 C10 table 55: derating values for t is/ t ih C ac150/dc100-based 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 0 C4 0 C4 0C4 8 4 16 12 24 20 32 30 40 46 0.8 0 C10 0 C10 0 C10 8 C2 16 6 24 14 32 24 40 40 0.7 0 C16 0 C16 0 C16 8 C8 16 0 24 8 32 18 40 34 0.6 C1 C26 C1 C26 C1 C26 7 C18 15 C10 23 C2 31 8 39 24 0.5 C10 C40 C10 C40 C10 C40 C2 C32 6 C24 14 C16 22 C6 30 10 0.4 C25 C60 C25 C60 C25 C60 C17 C52 C9 C44 C1 C36 7 C26 15 C10 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 56: derating values for t is/ t ih C ac135/dc100-based t is, 2.0 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 2 C4 2 C4 2C4 10 4 1812262034304246 0.8 3 C10 3 C10 3 C10 11 C2 19 6 27 14 35 24 43 40 0.7 6 C16 6 C16 6 C16 14 C8 22 0 30 8 38 18 46 34 0.6 9 C26 9 C26 9 C26 17 C18 25 C10 33 C2 41 8 49 24 0.5 5 C40 5 C40 5 C40 13 C32 21 C24 29 C16 37 C6 45 10 0.4 C3 C60 C3 C60 C3 C60 6 C52 14 C44 22 C36 30 C26 38 C10 table 57: derating values for t is/ t ih C ac125/dc100-based 2.0 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 4 C4 4 C4 4C4 12 4 2012282036304446 0.8 6 C10 6 C10 6 C10 14 C2 22 6 30 14 38 24 45 40 0.7 11 C16 11 C16 11 C16 19 C8 27 0 35 8 43 18 51 34 0.6 16 C26 16 C26 16 C26 24 C18 32 C10 40 C2 48 8 56 24 0.5 15 C40 15 C40 15 C40 23 C32 31 C24 39 C16 47 C6 55 10 0.4 13 C60 13 C60 13 C60 21 C52 29 C44 37 C36 45 C26 53 C10 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 58: minimum required time t vac above v ih(ac) or below v il(ac) for valid transition slew rate (v/ns) t vac at 175mv (ps) t vac at 150mv (ps) t vac at 135mv (ps) t vac at 125mv (ps) >2.0 75 175 168 173 2.0 57 170 168 173 1.5 50 167 145 152 1.0 38 130 100 110 0.9 34 113 85 96 0.8 29 93 66 79 0.7 22 66 42 56 0.6 note 1 30 10 27 0.5 note 1 note 1 note 1 note 1 <0.5 note 1 note 1 note 1 note 1 note: 1. rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 27: nominal slew rate and t vac for t is (command and address C clock) v ss setup slew rate rising signal setup slew rate falling signal ? tf ? tr == v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(dc)max nominal slew rate v ref to ac region t vac t vac dqs dqs# ck# ck t is t ih t is t ih nominal slew rate v ref to ac region v ref(dc) - v il(ac)max ? tf v ih(ac)min - v ref(dc) ? tr note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 28: nominal slew rate for t ih (command and address C clock) v ss hold slew rate falling signal hold slew rate rising signal ? tr ? tf = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate dc to v ref region dqs dqs# ck# ck t is t ih t is t ih dc to v ref region nominal slew rate v ref(dc) - v il(dc)max ? tr v ih(dc)min - v ref(dc) ? tf note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 29: tangent line for t is (command and address C clock) v ss setup slew rate rising signal setup slew rate falling signal = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(dc)max tangent line v ref to ac region nominal line t vac t vac dqs dqs# ck# ck t is t ih t is t ih v ref to ac region tangent line nominal line tangent line (v ih(dc)min - v ref(dc) ) tangent line (v ref(dc) - v il(ac)max ) ? tr ? tr ? tf ? tf note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 30: tangent line for t ih (command and address C clock) v ss hold slew rate falling signal = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il( dc)max v il( ac)max tangen t line dc to v ref region hold slew rate rising signal = dqs dqs# ck# ck t is t ih t is t ih dc to v ref region tangen t line nominal line nominal line tangent line (v ref(dc) - v il(dc)max ) tangent line (v ih(dc)min - v ref(dc) ) ? tr ? tr ? tr ? tf note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram command and address setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
data setup, hold, and derating the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet t ds (base) and t dh (base) values (see table 59 (page 99); values come from ta- ble 51 (page 71)) to the t ds and t dh derating values (see table 60 (page 100)), re- spectively. example: t ds (total setup time) = t ds (base) + t ds. for a valid transition, the input signal has to remain above/below v ih(ac) /v il(ac) for some time t vac (see table 64 (page 103)). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih(ac) /v il(ac) ) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih /v il(ac) . for slew rates that fall between the values listed in table 61 (page 100), the derating values may obtained by linear interpolation. setup ( t ds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup ( t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) -to-ac region, use the nominal slew rate for derating value (see figure 31 (page 104)). if the actual signal is later than the nominal slew rate line anywhere between the shaded v ref(dc) -to-ac region, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 33 (page 106)). hold ( t dh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . hold ( t dh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc-to-v ref(dc) region, use the nominal slew rate for derating value (see figure 32 (page 105)). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded dc-to-v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc-to-v ref(dc) region is used for derating val- ue (see figure 34 (page 107)). table 59: ddr3 data setup and hold values at 1 v/ns (dqs, dqs# at 2 v/ns) C ac/dc-based symbol 800 1066 1333 1600 1866 2133 unit reference t ds (base) ac175 75 25 C C C C ps v ih(ac) /v il(ac) t ds (base) ac150 125 75 30 10 C C ps v ih(ac) /v il(ac) t ds (base) ac135 165 115 60 40 68 53 ps v ih(ac) /v il(ac) t dh (base) dc100 150 100 65 45 70 55 ps v ih(dc) /v il(dc) slew rate referenced 1 1 1 1 2 2 v/ns 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 60: derating values for t ds/ t dh C ac175/dc100-based shaded cells indicate slew rate combinations not supported t ds, 2.0 88 50 88 50 88 50 1.5 59 34 59 34 59 34 67 42 1.0 000000881616 0.9 C2 C4 C2 C4 6 4 14 12 22 20 0.8 C6 C10 2 C2 10 6 18 14 26 24 0.7 C3 C8 5 0 13 8 21 18 29 34 0.6 C1 C10 7 C2 15 8 23 24 0.5 C11 C16 C2 C6 5 10 0.4 C30 C26 C22 C10 table 61: derating values for t ds/ t dh C ac150/dc100-based shaded cells indicate slew rate combinations not supported t ds, 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 34 58 42 1.0 000000881616 0.9 0 C4 0 C4 8 4 16 12 24 20 0.8 0 C10 8 C2 16 6 24 14 32 24 0.7 8 C8 16 0 24 8 32 18 40 34 0.6 15 C10 23 C2 31 8 39 24 0.5 14 C16 22 C6 30 10 0.4 7 C26 15 C10 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 62: derating values for t ds/ t dh C ac135/dc100-based at 1v/ns shaded cells indicate slew rate combinations not supported t ds, 2.0 68 50 68 50 68 50 1.5 45 34 45 34 45 34 53 42 1.0 000000881616 0.9 2 C4 2 C4 10 4 18 12 26 20 0.8 3 C10 11 C2 19 6 27 14 35 24 0.7 14 C8 22 0 30 8 38 18 46 34 0.6 25 C19 33 C2 41 8 49 24 0.5 29 C16 37 C6 45 C10 0.4 30 26 38 C10 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 63: derating values for t ds/ t dh C ac135/dc100-based at 2v/ns shaded cells indicate slew rate combinations not supported t ds, 4.0 34 25 34 25 34 25 3.5 29 21 29 21 29 21 29 21 3.0 23 17 23 17 23 17 23 17 23 17 2.5 14 10 14 10 14 10 14 10 14 10 2.0 0000000000 1.5 C23 C17 C23 C17 C23 C17 C23 C17 C15 C19 1.0 C68 C50 C68 C50 C68 C50 C60 C42 C52 C34 0.9 C66 C54 C66 C54 C58 C46 C50 C38 C42 C30 0.8 C64 60 C56 C52 C48 C40 C40 C36 C32 C26 0.7 C53 C59 C45 C51 C37 C43 C29 C33 C21 C17 0.6 C43 C61 C35 C53 C27 C43 C19 C27 0.5 C39 C66 C31 C56 C23 C40 0.4 C38 C76 C30 C60 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 64: required minimum time t vac above v ih(ac) (below v il(ac) ) for valid dq transition slew rate (v/ns) t vac at 175mv (ps) t vac at 150mv (ps) t vac at 135mv (ps) ddr3-800/1066 ddr3-800/1066/1333/1600 ddr3-800/1066/1333/1600 ddr3-1866 ddr3-2133 >2.0 75 105 113 93 73 2.0 57 105 113 93 73 1.5 50 80 90 70 50 1.0 38 30 45 25 5 0.9 34 13 30 note 1 note 1 0.8 29 note 1 11 note 1 note 1 0.7 note 1 note 1 note 1 note 1 note 1 0.6 note 1 note 1 note 1 note 1 note 1 0.5 note 1 note 1 note 1 note 1 note 1 <0.5 note 1 note 1 note 1 note 1 note 1 note: 1. rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 31: nominal slew rate and t vac for t ds (dq C strobe) v ss setup slew rate rising signal setup slew rate falling signal ? tf ? tr = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate v ref to ac region t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region nominal slew rate v ih(ac)min - v ref(dc) ? tr v ref(dc) - v il(ac)max ? tf note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 32: nominal slew rate for t dh (dq C strobe) v ss hold slew rate falling signal hold slew rate rising signal == v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate dc to v ref region t dh t ds dqs dqs# t dh t ds ck# ck dc to v ref region nominal slew rate v ref(dc) - v il(dc)max v il(dc)min - v ref(dc) ? tr ? tf ? tf ? tr note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 33: tangent line for t ds (dq C strobe) v ss setup slew rate rising signal setup slew rate falling signal = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangent line v ref to ac region nominal line t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region tangent line nominal line tangent line (v ref(dc) - v il(ac)max ) tangent line (v ih(ac)min - v ref(dc) ) ? tr ? tr ? tf ? tf note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 34: tangent line for t dh (dq C strobe) v ss hold slew rate falling signal ? tf ? tr = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangent line dc to v ref region hold slew rate rising signal = dqs dqs# ck# ck dc to v ref region tangent line nominal line nominal line tangent line (v ih(dc)min - v ref(dc) ) ? tf tangent line (v ref(dc) - v il(dc)max ) ? tr t ds t dh t ds t dh note: 1. the clock and the strobe are drawn on different time scales. 2gb: x4, x8, x16 ddr3 sdram data setup, hold, and derating pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
commands C truth tables table 65: truth table C command notes 1C5 apply to the entire table function symbol cke cs# ras# cas# we# ba [2:0] a n a12 a10 a[11, 9:0] notes prev. cycle next cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 6 self refresh exit srx l h h v v v v v v v v 6, 7 lh hh single-bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v h v bank activate act h h l l h h ba row address (ra) write bl8mrs, bc4mrs wr h h l h l l ba rfu v l ca 8 bc4otf wrs4 h h l h l l ba rfu l l ca 8 bl8otf wrs8 h h l h l l ba rfu h l ca 8 write with auto precharge bl8mrs, bc4mrs wrap h h l h l l ba rfu v h ca 8 bc4otf wraps4 h h l h l l ba rfu l h ca 8 bl8otf wraps8 h h l h l l ba rfu h h ca 8 read bl8mrs, bc4mrs rd h h l h l h ba rfu v l ca 8 bc4otf rds4 h h l h l h ba rfu l l ca 8 bl8otf rds8 h h l h l h ba rfu h l ca 8 read with auto precharge bl8mrs, bc4mrs rdap h h l h l h ba rfu v h ca 8 bc4otf rdaps4 h h l h l h ba rfu l h ca 8 bl8otf rdaps8 h h l h l h ba rfu h h ca 8 no operation nop h h h h h v v v v v 9 device deselected des h h h x x x x x x x x 10 power-down entry pde h l l h h h v v v v v 6 hv v v power-down exit pdx l h l h h h v v v v v 6, 11 hv v v zq calibration long zqcl h h l h h l x x x h x 12 zq calibration short zqcs h h l h h l x x x l x notes: 1. commands are defined by the states of cs#, ras#, cas#, we#, and cke at the rising edge of the clock. the msb of ba, ra, and ca are device-, density-, and configuration- dependent. 2gb: x4, x8, x16 ddr3 sdram commands C truth tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
2. reset# is enabled low and used only for asynchronous reset. thus, reset# must be held high during any normal operation. 3. the state of odt does not affect the states described in this table. 4. operations apply to the bank defined by the bank address. for mrs, ba selects one of four mode registers. 5. v means h or l (a defined logic level), and x means dont care. 6. see table 66 (page 110) for additional information on cke transition. 7. self refresh exit is asynchronous. 8. burst reads or writes cannot be terminated or interrupted. mrs (fixed) and otf bl/bc are defined in mr0. 9. the purpose of the nop command is to prevent the dram from registering any unwan- ted commands. a nop will not terminate an operation that is executing. 10. the des and nop commands perform similarly. 11. the power-down mode does not perform any refresh operations. 12. zq calibration long is used for either zqinit (first zqcl command during initializa- tion) or zqoper (zqcl command after initialization). 2gb: x4, x8, x16 ddr3 sdram commands C truth tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 66: truth table C cke notes 1C2 apply to the entire table; see table 65 (page 108) for additional command details current state 3 cke command 5 (ras#, cas#, we#, cs#) action 5 notes previous cycle 4 ( n - 1) present cycle 4 ( n ) power-down l l dont care maintain power-down l h des or nop power-down exit self refresh l l dont care maintain self refresh l h des or nop self refresh exit bank(s) active h l des or nop active power-down entry reading h l des or nop power-down entry writing h l des or nop power-down entry precharging h l des or nop power-down entry refreshing h l des or nop precharge power-down entry all banks idle h l des or nop precharge power-down entry 6 h l refresh self refresh notes: 1. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. t cke (min) means cke must be registered at multiple consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + t cke (min) + t ih. 3. current state = the state of the dram immediately prior to clock edge n . 4. cke ( n ) is the logic state of cke at clock edge n ; cke ( n - 1) was the state of cke at the previous clock edge. 5. command is the command registered at the clock edge (must be a legal command as defined in table 65 (page 108)). action is a result of command. odt does not affect the states described in this table and is not listed. 6. idle state = all banks are closed, no data bursts are in progress, cke is high, and all tim- ings from previous operations are satisfied. all self refresh exit and power-down exit pa- rameters are also satisfied. 2gb: x4, x8, x16 ddr3 sdram commands C truth tables pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
commands deselect the deselt (des) command (cs# high) prevents new commands from being execu- ted by the dram. operations already in progress are not affected. no operation the no operation (nop) command (cs# low) prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affec- ted. zq calibration long the zq calibration long (zqcl) command is used to perform the initial calibra- tion during a power-up initialization and reset sequence (see figure 43 (page 127)). this command may be issued at any time by the controller, depending on the system environment. the zqcl command triggers the calibration engine inside the dram. af- ter calibration is achieved, the calibrated values are transferred from the calibration en- gine to the dram i/o, which are reflected as updated r on and odt values. the dram is allowed a timing window defined by either t zqinit or t zqoper to perform a full calibration and transfer of values. when zqcl is issued during the initialization sequence, the timing parameter t zqinit must be satisfied. when initialization is com- plete, subsequent zqcl commands require the timing parameter t zqoper to be satis- fied. zq calibration short the zq calibration short (zqcs) command is used to perform periodic calibra- tions to account for small voltage and temperature variations. a shorter timing window is provided to perform the reduced calibration and transfer of values as defined by tim- ing parameter t zqcs. a zqcs command can effectively correct a minimum of 0.5% r on and r tt impedance error within 64 clock cycles, assuming the maximum sensitivities specified in table 37 (page 58) and table 38 (page 58). activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba[2:0] inputs selects the bank, and the address provided on inputs a[ n :0] selects the row. this row remains open (or active) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the address provided on inputs a[2:0] selects the starting column address, depending on the burst length and burst type selected (see burst order table for additional information). the value on input a10 determines whether auto precharge is used. if auto precharge is se- lected, the row being accessed will be precharged at the end of the read burst. if auto 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
precharge is not selected, the row will remain open for subsequent accesses. the value on input a12 (if enabled in the mode register) when the read command is issued de- termines whether bc4 (chop) or bl8 is used. after a read command is issued, the read burst may not be interrupted. table 67: read command summary function symbol cke cs# ras# cas# we# ba [3:0] a n a12 a10 a[11, 9:0] prev. cycle next cycle read bl8mrs, bc4mrs rd h l h l h ba rfu v l ca bc4otf rds4 h l h l h ba rfu l l ca bl8otf rds8 h l h l h ba rfu h l ca read with auto precharge bl8mrs, bc4mrs rdap h l h l h ba rfu v h ca bc4otf rdaps4 h l h l h ba rfu l h ca bl8otf rdaps8 h l h l h ba rfu h h ca write the write command is used to initiate a burst write access to an active row. the value on the ba[2:0] inputs selects the bank. the value on input a10 determines whether auto precharge is used. the value on input a12 (if enabled in the mr) when the write com- mand is issued determines whether bc4 (chop) or bl8 is used. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory. if the dm signal is registered high, the corresponding data inputs will be ignored and a write will not be executed to that byte/column location. table 68: write command summary function symbol cke cs# ras# cas# we# ba [3:0] a n a12 a10 a[11, 9:0] prev. cycle next cycle write bl8mrs, bc4mrs wr h l h l l ba rfu v l ca bc4otf wrs4 h l h l l ba rfu l l ca bl8otf wrs8 h l h l l ba rfu h l ca write with auto precharge bl8mrs, bc4mrs wrap h l h l l ba rfu v h ca bc4otf wraps4 h l h l l ba rfu l h ca bl8otf wraps8 h l h l l ba rfu h h ca 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
precharge the precharge command is used to de-activate the open row in a particular bank or in all banks. the bank(s) are available for a subsequent row access a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto pre- charge. a read or write command to a different bank is allowed during a concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether one or all banks are precharged. in the case where only one bank is precharged, inputs ba[2:0] se- lect the bank; otherwise, ba[2:0] are treated as dont care. after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period is determined by the last precharge command issued to the bank. refresh the refresh command is used during normal operation of the dram and is analo- gous to cas#-before-ras# (cbr) refresh or auto refresh. this command is nonpersis- tent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a dont care during a re- fresh command. the dram requires refresh cycles at an average interval of 7.8s (maximum when t c 85c or 3.9s maximum when t c 95c). the refresh period begins when the refresh command is registered and ends t rfc (min) later. to allow for improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refresh interval is provided. a maximum of eight refresh com- mands can be posted to any given dram, meaning that the maximum absolute interval between any refresh command and the next refresh command is nine times the maximum average interval refresh rate. self refresh may be entered with up to eight re- fresh commands being posted. after exiting self refresh (when entered with posted refresh commands), additional posting of refresh commands is allowed to the ex- tent that the maximum number of cumulative posted refresh commands (both pre- and post-self refresh) does not exceed eight refresh commands. the posting limit of eight refresh commands is a jedec specification; however, as long as all the required number of refresh commands are issued within the refresh period (64ms), exceeding the eight posted refresh commands is allowed. 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 35: refresh mode nop 1 nop 1 nop 1 pre ra bank(s) 3 ba ref nop 5 ref 2 nop 5 act nop 5 one bank all banks t ck t ch t cl ra t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 dont care indicates break in time scale valid 5 valid 5 valid 5 ck ck# command cke address a10 ba[2:0] dq 4 dm 4 dqs, dqs# 4 notes: 1. nop commands are shown for ease of illustration; other valid commands may be possi- ble at these times. cke must be active during the precharge, activate, and refresh commands, but may be inactive at other times (see power-down mode (page 175)). 2. the second refresh is not required, but two back-to-back refresh commands are shown. 3. dont care if a10 is high at this point; however, a10 must be high if more than one bank is active (must precharge all active banks). 4. for operations shown, dm, dq, and dqs signals are all dont care/high-z. 5. only nop and des commands are allowed after a refresh command and until t rfc (min) is satisfied. self refresh the self refresh command is used to retain data in the dram, even if the rest of the system is powered down. when in self refresh mode, the dram retains data without ex- ternal clocking. self refresh mode is also a convenient method used to enable/disable the dll as well as to change the clock frequency within the allowed synchronous oper- ating range (see input clock frequency change (page 119)). all power supply inputs (including v refca and v refdq ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. all power supply inputs (including v refca and v refdq ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. v refdq may float or not drive v ddq /2 while in self refresh mode under the following conditions: ?v ss < v refdq < v dd is maintained ?v refdq is valid and stable prior to cke going back high ? the first write operation may not occur earlier than 512 clocks after v refdq is valid 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
? all other self refresh mode exit timing requirements are met dll disable mode if the dll is disabled by the mode register (mr1[0] can be switched during initialization or later), the dram is targeted, but not guaranteed, to operate similarly to the normal mode, with a few notable exceptions: ? the dram supports only one value of cas latency (cl = 6) and one value of cas write latency (cwl = 6). ? dll disable mode affects the read data clock-to-data strobe relationship ( t dqsck), but not the read data-to-data strobe relationship ( t dqsq, t qh). special attention is required to line up the read data with the controller time domain when the dll is dis- abled. ? in normal operation (dll on), t dqsck starts from the rising clock edge al + cl cycles after the read command. in dll disable mode, t dqsck starts al + cl - 1 cy- cles after the read command. additionally, with the dll disabled, the value of t dqsck could be larger than t ck. the odt feature (including dynamic odt) is not supported during dll disable mode. the odt resistors must be disabled by continuously registering the odt ball low by programming r tt,nom mr1[9, 6, 2] and r tt(wr) mr2[10, 9] to 0 while in the dll disable mode. specific steps must be followed to switch between the dll enable and dll disable modes due to a gap in the allowed clock rates between the two modes ( t ck [avg] max and t ck [dll_dis] min, respectively). the only time the clock is allowed to cross this clock rate gap is during self refresh mode. thus, the required procedure for switching from the dll enable mode to the dll disable mode is to change frequency during self refresh: 1. starting from the idle state (all banks are precharged, all timings are fulfilled, odt is turned off, and r tt,nom and r tt(wr) are high-z), set mr1[0] to 1 to disable the dll. 2. enter self refresh mode after t mod has been satisfied. 3. after t cksre is satisfied, change the frequency to the desired clock rate. 4. self refresh may be exited when the clock is stable with the new frequency for t cksrx. after t xs is satisfied, update the mode registers with appropriate values. 5. the dram will be ready for its next command in the dll disable mode after the greater of t mrd or t mod has been satisfied. a zqcl command should be issued with appropriate timings met. 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 36: dll enable mode to dll disable mode command t0 t1 ta0 ta1 tb0 tc0 td0 td1 te0 te1 tf0 ck ck# odt 9 valid 1 dont care valid 1 sre 3 nop mrs 2 nop srx 4 mrs 5 valid 1 nop nop indicates break in time scale t mod t cksre t mod t xs t ckesr cke t cksrx 8 7 6 notes: 1. any valid command. 2. disable dll by setting mr1[0] to 1. 3. enter self refresh. 4. exit self refresh. 5. update the mode registers with the dll disable parameters setting. 6. starting with the idle state, r tt is in the high-z state. 7. change frequency. 8. clock must be stable t cksrx. 9. static low in the case that r tt,nom or r tt(wr) is enabled; otherwise, static low or high. a similar procedure is required for switching from the dll disable mode back to the dll enable mode. this also requires changing the frequency during self refresh mode (see figure 37 (page 117)). 1. starting from the idle state (all banks are precharged, all timings are fulfilled, odt is turned off, and r tt,nom and r tt(wr) are high-z), enter self refresh mode. 2. after t cksre is satisfied, change the frequency to the new clock rate. 3. self refresh may be exited when the clock is stable with the new frequency for t cksrx. after t xs is satisfied, update the mode registers with the appropriate val- ues. at a minimum, set mr1[0] to 0 to enable the dll. wait t mrd, then set mr0[8] to 1 to enable dll reset. 4. after another t mrd delay is satisfied, update the remaining mode registers with the appropriate values. 5. the dram will be ready for its next command in the dll enable mode after the greater of t mrd or t mod has been satisfied. however, before applying any com- mand or function requiring a locked dll, a delay of t dllk after dll reset must be satisfied. a zqcl command should be issued with the appropriate timings met. 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 37: dll disable mode to dll enable mode cke t0 ta0 ta1 tb0 tc0 tc1 td0 te0 tf0 tg0 ck ck# odt 10 sre 1 nop command nop srx 2 mrs 3 mrs 4 mrs 5 valid 6 valid dont care indicates break in time scale t cksre t cksrx 9 8 7 t xs t mrd t mrd t ckesr odtloff + 1 t ck th0 t dllk notes: 1. enter self refresh. 2. exit self refresh. 3. wait t xs, then set mr1[0] to 0 to enable dll. 4. wait t mrd, then set mr0[8] to 1 to begin dll reset. 5. wait t mrd, update registers (cl, cwl, and write recovery may be necessary). 6. wait t mod, any valid command. 7. starting with the idle state. 8. change frequency. 9. clock must be stable at least t cksrx. 10. static low in the case that r tt,nom or r tt(wr) is enabled; otherwise, static low or high. the clock frequency range for the dll disable mode is specified by the parameter t ck (dll_dis). due to latency counter and timing restrictions, only cl = 6 and cwl = 6 are supported. dll disable mode will affect the read data clock to data strobe relationship ( t dqsck) but not the data strobe to data relationship ( t dqsq, t qh). special attention is needed to line up read data to the controller time domain. compared to the dll on mode where t dqsck starts from the rising clock edge al + cl cycles after the read command, the dll disable mode t dqsck starts al + cl - 1 cycles after the read command. write operations function similarly between the dll enable and dll disable modes; however, odt functionality is not allowed with dll disable mode. 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 38: dll disable t dqsck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 dont care transitioning data valid nop read nop nop nop nop nop nop nop nop nop ck ck# command address di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq bl8 dll on dqs, dqs# dll on dq bl8 dll disable dqs, dqs# dll off dq bl8 dll disable dqs, dqs# dll off rl = al + cl = 6 (cl = 6, al = 0) cl = 6 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 t dqsck (dll_dis) min t dqsck (dll_dis) max rl (dll_dis) = al + (cl - 1) = 5 table 69: read electrical characteristics, dll disable mode parameter symbol min max unit access window of dqs from ck, ck# t dqsck (dll_dis) 1 10 ns 2gb: x4, x8, x16 ddr3 sdram commands pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
input clock frequency change when the ddr3 sdram is initialized, the clock must be stable during most normal states of operation. this means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate, except for what is allowed by the clock jitter and spread spectrum clocking (ssc) specifications. the input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. it is illegal to change the clock frequency outside of those two modes. for the self refresh mode con- dition, when the ddr3 sdram has been successfully placed into self refresh mode and t cksre has been satisfied, the state of the clock becomes a dont care. when the clock becomes a dont care, changing the clock frequency is permissible if the new clock frequency is stable prior to t cksrx. when entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met. the precharge power-down mode condition is when the ddr3 sdram is in precharge power-down mode (either fast exit mode or slow exit mode). either odt must be at a logic low or r tt,nom and r tt(wr) must be disabled via mr1 and mr2. this ensures r tt,nom and r tt(wr) are in an off state prior to entering precharge power-down mode, and cke must be at a logic low. a minimum of t cksre must occur after cke goes low before the clock frequency can change. the ddr3 sdram input clock frequency is al- lowed to change only within the minimum and maximum operating frequency speci- fied for the particular speed grade ( t ck [avg] min to t ck [avg] max). during the input clock frequency change, cke must be held at a stable low level. when the input clock frequency is changed, a stable clock must be provided to the dram t cksrx before pre- charge power-down may be exited. after precharge power-down is exited and t xp has been satisfied, the dll must be reset via the mrs. depending on the new clock fre- quency, additional mrs commands may need to be issued. during the dll lock time, r tt,nom and r tt(wr) must remain in an off state. after the dll lock time, the dram is ready to operate with a new clock frequency. 2gb: x4, x8, x16 ddr3 sdram input clock frequency change pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 119 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 39: change frequency during precharge power-down ck ck# command nop nop nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 ta0 tc0 tb0 t2 dont care t cke t xp mrs dll reset valid valid nop t ch t ih t is t cl tc1 td0 te1 td1 t cksre t ch b t cl b t ck b t ch b t cl b t ck b t ch b t cl b t ck b t cpded odt nop te0 previous clock frequency new clock frequency frequency change indicates break in time scale t ih t is t ih t is t dllk t aofpd/ t aof t cksrx high-z high-z notes: 1. applicable for both slow-exit and fast-exit precharge power-down modes. 2. t aofpd and t aof must be satisfied and outputs high-z prior to t1 (see on-die termina- tion (odt) (page 185) for exact requirements). 3. if the r tt,nom feature was enabled in the mode register prior to entering precharge power-down mode, the odt signal must be continuously registered low, ensuring r tt is in an off state. if the r tt,nom feature was disabled in the mode register prior to enter- ing precharge power-down mode, r tt will remain in the off state. the odt signal can be registered low or high in this case. 2gb: x4, x8, x16 ddr3 sdram input clock frequency change pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 120 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
write leveling for better signal integrity, ddr3 sdram memory modules have adopted fly-by topolo- gy for the commands, addresses, control signals, and clocks. write leveling is a scheme for the memory controller to adjust or de-skew the dqs strobe (dqs, dqs#) to ck rela- tionship at the dram with a simple feedback feature provided by the dram. write lev- eling is generally used as part of the initialization process, if required. for normal dram operation, this feature must be disabled. this is the only dram operation where the dqs functions as an input (to capture the incoming clock) and the dq function as outputs (to report the state of the clock). note that nonstandard odt schemes are re- quired. the memory controller using the write leveling procedure must have adjustable delay settings on its dqs strobe to align the rising edge of dqs to the clock at the dram pins. this is accomplished when the dram asynchronously feeds back the ck status via the dq bus and samples with the rising edge of dqs. the controller repeatedly delays the dqs strobe until a ck transition from 0 to 1 is detected. the dqs delay established by this procedure helps ensure t dqss, t dss, and t dsh specifications in systems that use fly-by topology by de-skewing the trace length mismatch. a conceptual timing of this procedure is shown in figure 40. figure 40: write leveling concept ck ck# source differential dqs differential dqs differential dqs dq dq ck ck# destination destination push dqs to capture 0C1 transition t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn ck ck# t0 t1 t2 t3 t4 t5 t6 tn dont care 11 0 0 2gb: x4, x8, x16 ddr3 sdram write leveling pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 121 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
when write leveling is enabled, the rising edge of dqs samples ck, and the prime dq outputs the sampled cks status. the prime dq for a x4 or x8 configuration is dq0 with all other dq (dq[7:1]) driving low. the prime dq for a x16 configuration is dq0 for the lower byte and dq8 for the upper byte. it outputs the status of ck sampled by ldqs and udqs. all other dq (dq[7:1], dq[15:9]) continue to drive low. two prime dq on a x16 enable each byte lane to be leveled independently. the write leveling mode register interacts with other mode registers to correctly config- ure the write leveling functionality. besides using mr1[7] to disable/enable write level- ing, mr1[12] must be used to enable/disable the output buffers. the odt value, burst length, and so forth need to be selected as well. this interaction is shown in table 70. it should also be noted that when the outputs are enabled during write leveling mode, the dqs buffers are set as inputs, and the dq are set as outputs. additionally, during write leveling mode, only the dqs strobe terminations are activated and deactivated via the odt ball. the dq remain disabled and are not affected by the odt ball. table 70: write leveling matrix note 1 applies to the entire table mr1[7] mr1[12] mr1[2, 6, 9] dram odt ball dram r tt,nom dram state case notes write leveling output buffers r tt,nom value dqs dq disabled see normal operations write leveling not enabled 0 enabled (1) disabled (1) n/a low off off dqs not receiving: not terminated prime dq high-z: not terminated other dq high-z: not terminated 12 , or 120 high on dqs not receiving: terminated by r tt prime dq high-z: not terminated other dq high-z: not terminated 2 enabled (0) n/a low off dqs receiving: not terminated prime dq driving ck state: not terminated other dq driving low: not terminated 33 , or 120 high on dqs receiving: terminated by r tt prime dq driving ck state: not terminated other dq driving low: not terminated 4 notes: 1. expected usage if used during write leveling: case 1 may be used when dram are on a dual-rank module and on the rank not being leveled or on any rank of a module not being leveled on a multislot system. case 2 may be used when dram are on any rank of a module not being leveled on a multislot system. case 3 is generally not used. case 4 is generally used when dram are on the rank that is being leveled. 2. since the dram dqs is not being driven (mr1[12] = 1), dqs ignores the input strobe, and all r tt,nom values are allowed. this simulates a normal standby state to dqs. 3. since the dram dqs is being driven (mr1[12] = 0), dqs captures the input strobe, and only some r tt,nom values are allowed. this simulates a normal write state to dqs. 2gb: x4, x8, x16 ddr3 sdram write leveling pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 122 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
write leveling procedure a memory controller initiates the dram write leveling mode by setting mr1[7] to 1, as- suming the other programable features (mr0, mr1, mr2, and mr3) are first set and the dll is fully reset and locked. the dq balls enter the write leveling mode going from a high-z state to an undefined driving state, so the dq bus should not be driven. during write leveling mode, only the nop or des commands are allowed. the memory con- troller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting mr1[12] to 1 in the other ranks. the memory controller may assert odt after a t mod delay, as the dram will be ready to process the odt tran- sition. odt should be turned on prior to dqs being driven low by at least odtlon delay (wl - 2 t ck), provided it does not violate the aforementioned t mod delay require- ment. the memory controller may drive dqs low and dqs# high after t wldqsen has been satisfied. the controller may begin to toggle dqs after t wlmrd (one dqs toggle is dqs transitioning from a low state to a high state with dqs# transitioning from a high state to a low state, then both transition back to their original states). at a mini- mum, odtlon and t aon must be satisfied at least one clock prior to dqs toggling. after t wlmrd and a dqs low preamble ( t wpre) have been satisfied, the memory controller may provide either a single dqs toggle or multiple dqs toggles to sample ck for a given dqs-to-ck skew. each dqs toggle must not violate t dqsl (min) and t dqsh (min) specifications. t dqsl (max) and t dqsh (max) specifications are not applicable during write leveling mode. the dqs must be able to distinguish the cks rising edge within t wls and t wlh. the prime dq will output the cks status asynchronously from the associated dqs rising edge ck capture within t wlo. the remaining dq that always drive low when dqs is toggling must be low within t wloe after the first t wlo is sat- isfied (the prime dq going low). as previously noted, dqs is an input and not an out- put during this process. figure 41 (page 124) depicts the basic timing parameters for the overall write leveling procedure. the memory controller will most likely sample each applicable prime dq state and de- termine whether to increment or decrement its dqs delay setting. after the memory controller performs enough dqs toggles to detect the cks 0-to-1 transition, the memo- ry controller should lock the dqs delay setting for that dram. after locking the dqs setting is locked, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). 2gb: x4, x8, x16 ddr3 sdram write leveling pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 123 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 41: write leveling sequence ck ck# command t1 t2 early remaining dq late remaining dq t wloe nop 2 nop mrs 1 nop nop nop nop nop nop nop nop nop t wls t wlh dont care undefined driving mode indicates break in time scale prime dq 5 differential dqs 4 odt t mod t dqsl 3 t dqsl 3 t dqsh 3 t dqsh 3 t wlo t wlmrd t wldqsen t wlo t wlo t wlo notes: 1. mrs: load mr1 to enter write leveling mode. 2. nop: nop or des. 3. dqs, dqs# needs to fulfill minimum pulse width requirements t dqsh (min) and t dqsl (min) as defined for regular writes. the maximum pulse width is system-dependent. 4. differential dqs is the differential data strobe (dqs, dqs#). timing reference points are the zero crossings. the solid line represents dqs; the dotted line represents dqs#. 5. dram drives leveling feedback on a prime dq (dq0 for x4 and x8). the remaining dq are driven low and remain in this state throughout the leveling procedure. 2gb: x4, x8, x16 ddr3 sdram write leveling pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 124 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
write leveling mode exit procedure after the dram are leveled, they must exit from write leveling mode before the normal mode can be used. figure 42 depicts a general procedure for exiting write leveling mode. after the last rising dqs (capturing a 1 at t0), the memory controller should stop driving the dqs signals after t wlo (max) delay plus enough delay to enable the memo- ry controller to capture the applicable prime dq state (at ~tb0). the dq balls become undefined when dqs no longer remains low, and they remain undefined until t mod after the mrs command (at te1). the odt input should be de-asserted low such that odtloff (min) expires after the dqs is no longer driving low. when odt low satisfies t is, odt must be kept low (at ~tb0) until the dram is ready for either another rank to be leveled or until the normal mode can be used. after dqs termination is switched off, write level mode should be disabled via the mrs command (at tc2). after t mod is satisfied (at te1), any valid com- mand may be registered by the dram. some mrs commands may be issued after t mrd (at td1). figure 42: write leveling exit procedure nop ck t0 t1 t2 ta0 tb0 tc0 tc1 tc2 td0 td1 te0 te1 ck# command odt r tt(dq) nop nop nop nop nop nop mrs nop nop address mr1 valid valid valid valid dont care transitioning r tt dqs, r tt dqs# r tt,nom undefined driving mode t aof (max) t mrd indicates break in time scale dqs, dqs# ck = 1 dq t is t aof (min) t mod t wlo + t wloe odtloff note: 1. the dq result, = 1, between ta0 and tc0, is a result of the dqs, dqs# signals capturing ck high just after the t0 state. 2gb: x4, x8, x16 ddr3 sdram write leveling pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 125 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
initialization the following sequence is required for power-up and initialization, as shown in fig- ure 43 (page 127): 1. apply power. reset# is recommended to be below 0.2 v ddq during power ramp to ensure the outputs remain disabled (high-z) and odt off (r tt is also high-z). all other inputs, including odt, may be undefined. during power-up, either of the following conditions may exist and must be met: ? condition a: Cv dd and v ddq are driven from a single-power converter output and are ramped with a maximum delta voltage between them of v 300mv. slope re- versal of any power supply signal is allowed. the voltage levels on all balls oth- er than v dd , v ddq , v ss , v ssq must be less than or equal to v ddq and v dd on one side, and must be greater than or equal to v ssq and v ss on the other side. C both v dd and v ddq power supplies ramp to v dd,min and v ddq,min within t v ddpr = 200ms. Cv refdq tracks v dd 0.5, v refca tracks v dd 0.5. Cv tt is limited to 0.95v when the power ramp is complete and is not applied directly to the device; however, t vtd should be greater than or equal to 0 to avoid device latchup. ? condition b: Cv dd may be applied before or at the same time as v ddq . Cv ddq may be applied before or at the same time as v tt , v refdq , and v refca . C no slope reversals are allowed in the power supply ramp for this condition. 2. until stable power, maintain reset# low to ensure the outputs remain disabled (high-z). after the power is stable, reset# must be low for at least 200s to be- gin the initialization process. odt will remain in the high-z state while reset# is low and until cke is registered high. 3. cke must be low 10ns prior to reset# transitioning high. 4. after reset# transitions high, wait 500s (minus one clock) with cke low. 5. after the cke low time, cke may be brought high (synchronously) and only nop or des commands may be issued. the clock must be present and valid for at least 10ns (and a minimum of five clocks) and odt must be driven low at least t is prior to cke being registered high. when cke is registered high, it must be continuously registered high until the full initialization process is complete. 6. after cke is registered high and after t xpr has been satisfied, mrs commands may be issued. issue an mrs (load mode) command to mr2 with the applicable settings (provide low to ba2 and ba0 and high to ba1). 7. issue an mrs command to mr3 with the applicable settings. 8. issue an mrs command to mr1 with the applicable settings, including enabling the dll and configuring odt. 9. issue an mrs command to mr0 with the applicable settings, including a dll re- set command. t dllk (512) cycles of clock input are required to lock the dll. 10. issue a zqcl command to calibrate r tt and r on values for the process voltage temperature (pvt). prior to normal operation, t zqinit must be satisfied. 11. when t dllk and t zqinit have been satisfied, the ddr3 sdram will be ready for normal operation. 2gb: x4, x8, x16 ddr3 sdram initialization pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 126 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 43: initialization sequence cke r tt ba[2:0] all voltage supplies valid and stable t = 200s (min) dm dqs address a10 ck ck# t cl command nop t0 ta0 dont care t cl t is t ck odt dq tb0 t dllk mr1 with dll enable mr0 with dll reset t mrd t mod mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code valid valid valid valid normal operation mr2 mr3 t mrd t mrd mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td0 v tt v ref v ddq v dd reset# t = 500s (min) t cksrx stable and valid clock valid power-up ramp t (max) = 200ms dram ready for external commands t1 t zqinit zq calibration a10 = h zqcl t is see power-up conditions in the initialization sequence text, set up 1 t xpr valid t ioz = 20ns indicates break in time scale t (min) = 10ns t vtd 2gb: x4, x8, x16 ddr3 sdram initialization pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 127 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
mode registers mode registers (mr0Cmr3) are used to define various modes of programmable opera- tions of the ddr3 sdram. a mode register is programmed via the mode register set (mrs) command during initialization, and it retains the stored information (except for mr0[8], which is self-clearing) until it is reprogrammed, reset# goes low, the device loses power. contents of a mode register can be altered by re-executing the mrs command. even if the user wants to modify only a subset of the mode registers variables, all variables must be programmed when the mrs command is issued. reprogramming the mode register will not alter the contents of the memory array, provided it is performed cor- rectly. the mrs command can only be issued (or re-issued) when all banks are idle and in the precharged state ( t rp is satisfied and no data bursts are in progress). after an mrs com- mand has been issued, two parameters must be satisfied: t mrd and t mod. the control- ler must wait t mrd before initiating any subsequent mrs commands. figure 44: mrs to mrs command timing ( t mrd) valid valid mrs 1 mrs 2 nop nop nop nop t0 t1 t2 ta0 ta1 ta2 ck# ck command address cke 3 dont care indicates break in time scale t mrd notes: 1. prior to issuing the mrs command, all banks must be idle and precharged, t rp (min) must be satisfied, and no data bursts can be in progress. 2. t mrd specifies the mrs to mrs command minimum cycle time. 3. cke must be registered high from the mrs command until t mrspden (min) (see pow- er-down mode (page 175)). 4. for a cas latency change, t xpdll timing must be met before any non-mrs command. the controller must also wait t mod before initiating any non-mrs commands (exclud- ing nop and des). the dram requires t mod in order to update the requested features, with the exception of dll reset, which requires additional time. until t mod has been satisfied, the updated features are to be assumed unavailable. 2gb: x4, x8, x16 ddr3 sdram mode registers pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 128 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 45: mrs to nonmrs command timing ( t mod) valid valid mrs non mrs nop nop nop nop t0 t1 t2 ta0 ta1 ta2 ck# ck command address cke valid old setting new setting dont care indicates break in time scale t mod updating setting notes: 1. prior to issuing the mrs command, all banks must be idle (they must be precharged, t rp must be satisfied, and no data bursts can be in progress). 2. prior to ta2 when t mod (min) is being satisfied, no commands (except nop/des) may be issued. 3. if r tt was previously enabled, odt must be registered low at t0 so that odtl is satis- fied prior to ta1. odt must also be registered low at each rising ck edge from t0 until t modmin is satisfied at ta2. 4. cke must be registered high from the mrs command until t mrspden (min), at which time power-down may occur (see power-down mode (page 175)). mode register 0 (mr0) the base register, mode register 0 (mr0), is used to define various ddr3 sdram modes of operation. these definitions include the selection of a burst length, burst type, cas latency, operating mode, dll reset, write recovery, and precharge power-down mode (see figure 46 (page 130)). burst length burst length is defined by mr0[1:0]. read and write accesses to the ddr3 sdram are burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed mode), or selectable using a12 during a read/write command (on-the-fly). the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when mr0[1:0] is set to 01 during a read/write command, if a12 = 0, then bc4 (chop) mode is selected. if a12 = 1, then bl8 mode is selected. specific timing diagrams, and turnaround between read/write, are shown in the read/write sections of this document. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a[ i :2] when the burst length is set to 4 and by a[ i :3] when the burst length is set to 8 (where a i is the most significant column address bit for a given config- uration). the remaining (least significant) address bit(s) is (are) used to select the start- 2gb: x4, x8, x16 ddr3 sdram mode register 0 (mr0) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 129 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
ing location within the block. the programmed burst length applies to both read and write bursts. figure 46: mode register 0 (mr0) definitions cl bl cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 0 (mr0) address bus 976543 8210 a10 a12 a11 a14 ba0 10 11 12 13 m3 0 1 read burst type sequential (nibble) interleaved cas latency reserved 5 6 7 8 9 10 11 12 13 m4 0 1 0 1 0 1 0 1 0 1 m2 0 0 0 0 0 0 0 0 1 1 m5 0 0 1 1 0 0 1 1 0 0 m6 0 0 0 0 1 1 1 1 0 0 15 dll write recovery 16 5 6 7 8 10 12 14 wr 0 1 0 m12 0 1 precharge pd dll off (slow exit) dll on (fast exit) ba1 16 0 ba2 17 0 1 burst length fixed bl8 4 or 8 (on-the-fly via a12) fixed bc4 (chop) reserved m0 0 1 0 1 m1 0 0 1 1 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 m15 0 1 0 1 m16 0 0 1 1 mode register mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) mode register 3 (mr3) a13 14 0 1 0 1 m8 0 1 dll reset no yes 01 1 014 note: 1. mr0[17, 14, 13, 7] are reserved for future use and must be programmed to 0. burst type accesses within a given burst may be programmed to either a sequential or an inter- leaved order. the burst type is selected via mr0[3] (see figure 46 (page 130)). the order- ing of accesses within a burst is determined by the burst length, the burst type, and the starting column address. ddr3 only supports 4-bit burst chop and 8-bit burst access modes. full interleave address ordering is supported for reads, while writes are re- stricted to nibble (bc4) or word (bl8) boundaries. 2gb: x4, x8, x16 ddr3 sdram mode register 0 (mr0) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 130 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 71: burst order burst length read/ write starting column address (a[2, 1, 0]) burst type = sequential (decimal) burst type = interleaved (decimal) notes 4 read 0 0 0 0, 1, 2, 3, z, z, z, z 0, 1, 2, 3, z, z, z, z 1, 2 0 0 1 1, 2, 3, 0, z, z, z, z 1, 0, 3, 2, z, z, z, z 1, 2 0 1 0 2, 3, 0, 1, z, z, z, z 2, 3, 0, 1, z, z, z, z 1, 2 0 1 1 3, 0, 1, 2, z, z, z, z 3, 2, 1, 0, z, z, z, z 1, 2 1 0 0 4, 5, 6, 7, z, z, z, z 4, 5, 6, 7, z, z, z, z 1, 2 1 0 1 5, 6, 7, 4, z, z, z, z 5, 4, 7, 6, z, z, z, z 1, 2 1 1 0 6, 7, 4, 5, z, z, z, z 6, 7, 4, 5, z, z, z, z 1, 2 1 1 1 7, 4, 5, 6, z, z, z, z 7, 6, 5, 4, z, z, z, z 1, 2 write 0 v v 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1, 3, 4 1 v v 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 1, 3, 4 8 read 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1 write v v v 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3 notes: 1. internal read and write operations start at the same point in time for bc4 as they do for bl8. 2. z = data and strobe output drivers are in tri-state. 3. v = a valid logic level (0 or 1), but the respective input buffer ignores level-on input pins. 4. x = dont care. dll reset dll reset is defined by mr0[8] (see figure 46 (page 130)). programming mr0[8] to 1 activates the dll reset function. mr0[8] is self-clearing, meaning it returns to a value of 0 after the dll reset function has been initiated. anytime the dll reset function is initiated, cke must be high and the clock held stable for 512 ( t dllk) clock cycles before a read command can be issued. this is to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in invalid output timing specifications, such as t dqsck timings. write recovery write recovery time is defined by mr0[11:9] (see figure 46 (page 130)). write recovery values of 5, 6, 7, 8, 10, 12, or 14 may be used by programming mr0[11:9]. the user is 2gb: x4, x8, x16 ddr3 sdram mode register 0 (mr0) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 131 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
required to program the correct value of write recovery, which is calculated by dividing t wr (ns) by t ck (ns) and rounding up a noninteger value to the next integer: wr (cycles) = roundup ( t wr [ns]/ t ck [ns]). precharge power-down (precharge pd) the precharge power-down (pd) bit applies only when precharge power-down mode is being used. when mr0[12] is set to 0, the dll is off during precharge power-down, pro- viding a lower standby current mode; however, t xpdll must be satisfied when exiting. when mr0[12] is set to 1, the dll continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, t xp must be sat- isfied when exiting (see power-down mode (page 175)). cas latency (cl) the cl is defined by mr0[6:4], as shown in figure 46 (page 130). cas latency is the de- lay, in clock cycles, between the internal read command and the availability of the first bit of output data. the cl can be set to 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14. ddr3 sdram do not support half-clock latencies. examples of cl = 6 and cl = 8 are shown below. if an internal read command is regis- tered at clock edge n , and the cas latency is m clocks, the data will be available nomi- nally coincident with clock edge n + m. table 46 (page 66) through table 49 (page 69) indicate the cls supported at various operating frequencies. figure 47: read latency read nop nop nop nop nop nop nop ck ck# command dq dqs, dqs# dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 dont care ck ck# command dq read nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 di n + 3 di n + 1 di n + 2 di n + 4 di n di n nop nop al = 0, cl = 8 al = 0, cl = 6 transitioning data notes: 1. for illustration purposes, only cl = 6 and cl = 8 are shown. other cl values are possible. 2. shown with nominal t dqsck and nominal t dsdq. 2gb: x4, x8, x16 ddr3 sdram mode register 0 (mr0) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 132 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
mode register 1 (mr1) the mode register 1 (mr1) controls additional features and functions not available in the other mode registers: dll enable/disable, output drive strength, output ena- ble/disable (q off), tdqs enable/disable (x8 configuration only), on-die termi- nation (odt) resistance value r tt,nom , write leveling, and posted cas additive la- tency (al). these features and functions are controlled via the bits shown in the figure below. the mr1 register is programmed via the mrs command and retains the stored information until it is reprogrammed, reset# goes low, or the device loses power. re- programming the mr1 register will not alter the contents of the memory array, provided it is reprogrammed correctly. the mr1 register must be loaded when all banks are idle and no bursts are in progress. the controller must satisfy the specified timing parameters t mrd and t mod before ini- tiating a subsequent operation. figure 48: mode register 1 (mr1) definition al r tt q off a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 1 (mr1) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 m0 0 1 dll enable enable (normal) disable m5 0 0 1 1 output drive strength rzq/6 (40 nom) rzq/7 (34 nom) reserved reserved 14 wl 0 1 1 ods dll r tt tdqs m12 0 1 q off enabled disabled ba2 15 0 1 m7 0 1 write leveling disable (normal) enable additive latency (al) disabled (al = 0) al = cl - 1 al = cl - 2 reserved m3 0 1 0 1 m4 0 0 1 1 r tt ods m1 0 1 0 1 a13 a14 16 17 0 0 1 m11 0 1 tdqs disabled enabled 0 1 0 1 r tt,nom (odt) 2 non-writes r tt,nom disabled rzq/4 (60 nom) rzq/2 (120 nom) rzq/6 (40 nom) rzq/12 (20 nom) rzq/8 (30 nom) reserved reserved r tt,nom (odt) 3 writes r tt,nom disabled rzq/4 (60 nom) rzq/2 (120 nom) rzq/6 (40 nom) n/a n/a reserved reserved m2 0 1 0 1 0 1 0 1 m6 0 0 1 1 0 0 1 1 m9 0 0 0 0 1 1 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) m15 0 1 0 1 m16 0 0 1 1 notes: 1. mr1[17, 14, 13, 10, 8] are reserved for future use and must be programmed to 0. 2. during write leveling, if mr1[7] and mr1[12] are 1, then all r tt,nom values are available for use. 3. during write leveling, if mr1[7] is 1, but mr1[12] is 0, then only r tt,nom write values are available for use. dll enable/disable the dll may be enabled or disabled by programming mr1[0] during the load mode command (see figure 48 (page 133)). the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation, after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using the appropriate load mode command. 2gb: x4, x8, x16 ddr3 sdram mode register 1 (mr1) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 133 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
if the dll is enabled prior to entering self refresh mode, the dll is automatically disa- bled when entering the self refresh operation and is automatically re-enabled and reset upon exit of the self refresh operation. if the dll is disabled prior to entering self refresh mode, the dll remains disabled, even upon exit of the self refresh oper- ation until it is re-enabled and reset. the dram is not tested to checknor does micron warrant compliance withnormal mode timings or functionality when the dll is disabled. an attempt has been made to have the dram operate in the normal mode where reasonably possible when the dll has been disabled; however, by industry standard, a few known exceptions are defined: ? odt is not allowed to be used. ? the output data is no longer edge-aligned to the clock. ? cl and cwl can only be six clocks. when the dll is disabled, timing and functionality can vary from the normal operation specifications when the dll is enabled (see dll disable mode (page 115)). disabling the dll also implies the need to change the clock frequency (see input clock frequen- cy change (page 119)). output drive strength the ddr3 sdram uses a programmable impedance output buffer. the drive strength mode register setting is defined by mr1[5, 1]. rzq/7 (34 [nom]) is the primary output driver impedance setting for ddr3 sdram devices. to calibrate the output driver im- pedance, an external precision resistor (rzq) is connected between the zq ball and v ssq . the value of the resistor must be 240 r the output impedance is set during initialization. additional impedance calibration up- dates do not affect device operation, and all data sheet timings and current specifica- tions are met during an update. to meet the 34 specification, the output drive strength must be set to 34 during initi- alization. to obtain a calibrated output driver impedance after power-up, the ddr3 sdram needs a calibration command that is part of the initialization and reset proce- dure. output enable/disable the output enable/disable function is defined by mr1[12] (see figure 48 (page 133)). when enabled (mr1[12] = 0), all outputs (dq, dqs, dqs#) function when in the normal mode of operation. when disabled (mr1[12] = 1), all ddr3 sdram out- puts (dq and dqs, dqs#) are high-z. the output disable feature is intended to be used during i dd characterization of the read current and during t dqss margining (write leveling) only. tdqs enable termination data strobe (tdqs) is a function of the x8 ddr3 sdram configuration that provides termination resistance r tt , and can be useful in some system configura- tions. tdqs is not supported in x4 or x16 configurations. when enabled via the mode register (mr1[11]), r tt applied to dqs and dqs# is also applied to tdqs and tdqs#. in contrast to the rdqs function of ddr2 sdram, ddr3s tdqs provides the termina- tion resistance r tt only. the output data strobe function of rdqs is not provided by tdqs; thus, r on does not apply to tdqs and tdqs#. the tdqs and dm functions 2gb: x4, x8, x16 ddr3 sdram mode register 1 (mr1) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 134 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
share the same ball. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is pro- vided, and the tdqs# ball is not used. the tdqs function is available in the x8 ddr3 sdram configuration only and must be disabled via the mode register for the x4 and x16 configurations. on-die termination (odt) on-die termination (odt) resistance r tt,nom is defined by mr1[9, 6, 2] (see figure 48 (page 133)). the r tt termination resistance value applies to the dq, dm, dqs, dqs#, and tdqs, tdqs# balls. ddr3 supports multiple r tt termination resistance values based on rzq/ n where n can be 2, 4, 6, 8, or 12 and rzq is 240 unlike ddr2, ddr3 odt must be turned off prior to reading data out and must remain off during a read burst. r tt,nom termination is allowed any time after the dram is ini- tialized, calibrated, and not performing read accesses, or when it is not in self refresh mode. additionally, write accesses with dynamic odt (r tt(wr) ) enabled temporarily re- places r tt,nom with r tt(wr) . the effective termination, r tt(eff) , may be different from r tt targeted due to nonlinear- ity of the termination. for r tt(eff) values and calculations, see on-die termination (odt) (page 185). the odt feature is designed to improve signal integrity of the memory channel by ena- bling the ddr3 sdram controller to independently turn on/off odt for any or all devi- ces. the odt input control pin is used to determine when r tt is turned on (odtlon) and off (odtloff), assuming odt has been enabled via mr1[9, 6, 2]. timings for odt are detailed in on-die termination (odt) (page 185). write leveling the write leveling function is enabled by mr1[7] (see figure 48 (page 133)). write leveling is used (during initialization) to de-skew the dqs strobe to clock offset as a re- sult of fly-by topology designs. for better signal integrity, ddr3 sdram memory mod- ules adopted fly-by topology for the commands, addresses, control signals, and clocks. the fly-by topology benefits from a reduced number of stubs and their lengths. howev- er, fly-by topology induces flight time skews between the clock and dqs strobe (and dq) at each dram on the dimm. controllers will have a difficult time maintaining t dqss, t dss, and t dsh specifications without supporting write leveling in systems that use fly-by topology-based modules. write leveling timing and detailed operation infor- mation is provided in write leveling (page 121). posted cas additive latency (al) posted cas additive latency (al) is supported to make the command and data bus effi- cient for sustainable bandwidths in ddr3 sdram. mr1[4, 3] define the value of al (see figure 49 (page 136)). mr1[4, 3] enable the user to program the ddr3 sdram with al = 0, cl - 1, or cl - 2. with this feature, the ddr3 sdram enables a read or write command to be issued after the activate command for that bank prior to t rcd (min). the only restriction is activate to read or write + al t rcd (min) must be satisfied. assuming t rcd (min) = cl, a typical application using this feature sets al = cl - 1 t ck = t rcd (min) - 1 t ck. the read or write command is held for the time of the al before it is released 2gb: x4, x8, x16 ddr3 sdram mode register 1 (mr1) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 135 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
internally to the ddr3 sdram device. read latency (rl) is controlled by the sum of the al and cas latency (cl), rl = al + cl. write latency (wl) is the sum of cas write latency and al, wl = al + cwl (see mode register 2 (mr2) (page 137)). exam- ples of read and write latencies are shown in figure 49 (page 136) and figure 50 (page 137). figure 49: read latency (al = 5, cl = 6) ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop read n t13 nop do n + 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates break in time scale transitioning data t2 nop 2gb: x4, x8, x16 ddr3 sdram mode register 1 (mr1) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 136 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
mode register 2 (mr2) the mode register 2 (mr2) controls additional features and functions not available in the other mode registers. these addional functions are cas write latency (cwl), au- to self refresh (asr), self refresh temperature (srt), and dynamic odt (r tt(wr) ). these functions are controlled via the bits shown in the figure below. mr2 is programmed via the mrs command and will retain the stored information until it is programmed again or the device loses power. reprogramming the mr2 register will not alter the contents of the memory array, provided it is reprogrammed correctly. the mr2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time t mrd and t mod before initiating a subse- quent operation. figure 50: mode register 2 (mr2) definition m15 0 1 0 1 m16 0 0 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 2 (mr2) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 15 0 cwl 0 1 0 1 ba2 asr 2 16 17 1 0 1 a13 a14 0 1 0 1 0 1 0 1 0 1 0 1 srt r tt(wr) m6 0 1 auto self refresh (optional) disabled: manual enabled: automatic m7 0 1 self refresh temperature normal (0c to 85c) extended (0c to 95c) cas write latency (cwl) 5 ck ( t ck ? 2.5ns) 6 ck (2.5ns > t ck ? 1.875ns) 7 ck (1.875ns > t ck ? 1.5ns) 8 ck (1.5ns > t ck ? 1.25ns) 9 ck (1.25ns > t ck ? 1.07ns) 10 ck (1.071ns > t ck ? 0.938ns) reserved reserved m3 0 1 0 1 0 1 0 1 m4 0 0 1 1 0 0 1 1 m5 0 0 0 0 1 1 1 1 m9 0 1 0 1 m10 0 0 1 1 dynamic odt (r tt(wr) ) r tt(wr) disabled rzq/4 (60 nom) rzq/2 (120 nom) reserved notes: 1. mr2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 2. on die revision a, asr is not available; mr2[6] must be programmed to 0 and, if operat- ing in self refresh mode above 85c, mr2[7] (srt) must be used. cas write latency (cwl) cas write latency (cwl) is defined by mr2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. cwl must be cor- rectly set to the corresponding operating clock frequency (see figure 50). the overall write latency (wl) is equal to cwl + al (figure 48 (page 133)). 2gb: x4, x8, x16 ddr3 sdram mode register 2 (mr2) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 137 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 51: cas write latency ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop write n t13 nop di n + 3 di n + 2 di n + 1 t14 nop di n t rcd (min) nop al = 5 t11 indicates break in time scale wl = al + cwl = 11 transitioning data t2 cwl = 6 auto self refresh (asr) mode register mr2[6] is used to disable/enable the asr function. when asr is disabled, the self refresh modes refresh rate is assumed to be at the normal 85c limit (some- times referred to as 1x refresh rate). in the disabled mode, asr requires the user to en- sure the dram never exceeds a case temperature ( t c ) of 85c while in self refresh, un- less the user enables the srt function when t c is between 85c and 95c. enabling asr assumes the dram self refresh rate is changed automatically from 1x to 2x when t c exceeds 85c. this enables the user to operate the dram beyond the stand- ard 85c limit up to the optional extended temperature range of 95c while in self re- fresh mode. the standard self refresh current test specifies test conditions for normal t c (85c) only, meaning that if asr is enabled, the standard self refresh current specifications do not apply (see extended temperature usage (page 174)). self refresh temperature (srt) mode register mr2[7] is used to disable/enable the srt function. when srt is disabled, the self refresh modes refresh rate is assumed to be at the normal 85c limit (some- times referred to as 1x refresh rate). in the disabled mode, srt requires the user to en- sure the dram never exceeds a t c of 85c while in self refresh mode, unless the user enables asr. when srt is enabled, the dram self refresh is changed internally from 1x to 2x, regard- less of t c . this enables the user to operate the dram beyond the standard 85c limit up to the optional extended temperature range of 95c while in self refresh mode. the standard self refresh current test specifies test conditions for normal t c (85c) only, meaning that if srt is enabled, the standard self refresh current specifications do not apply (see extended temperature usage (page 174)). 2gb: x4, x8, x16 ddr3 sdram mode register 2 (mr2) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 138 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
srt versus asr if the normal t c limit of 85c is not exceeded, then neither srt nor asr is required, and both can be disabled throughout operation. however, if the extended temperature op- tion of 95c is needed, the user is required to provide a 2x refresh rate during manual refresh and to enable either the srt or the asr to ensure self refresh is performed at the 2x rate. srt forces the dram to switch the internal self refresh rate from 1x to 2x. self refresh is performed at the 2x refresh rate regardless of the case temperature. asr automatically switches the drams internal self refresh rate from 1x to 2x. howev- er, while in self refresh mode, asr enables the refresh rate to automatically adjust be- tween 1x and 2x over the supported temperature range. one other disadvantage of asr is the dram cannot always switch from a 1x to 2x refresh rate at an exact t c of 85c. although the dram will support data integrity when it switches from a 1x to 2x refresh rate, it may switch at a temperature lower than 85c. since only one mode is necessary, srt and asr cannot be enabled at the same time. dynamic on-die termination (odt) the dynamic odt (r tt(wr) ) feature is defined by mr2[10, 9]. dynamic odt is enabled when a value is selected for the dynamic odt resistance r tt(wr) . this new ddr3 sdram feature enables the odt termination resistance value to change without issu- ing an mrs command, essentially changing the odt termination on-the-fly. with dynamic odt (r tt(wr) ) enabled, the dram switches from nominal odt (r tt,nom ) to dynamic odt (r tt(wr) ) when beginning a write burst, and subsequently switches back to normal odt (r tt,nom ) at the completion of the write burst. if r tt,nom is disa- bled, the r tt,nom value will be high-z. special timing parameters must be adhered to when dynamic odt (r tt(wr) ) is enabled: odtlcnw, odtlcwn4, odtlcwn8, odth4, odth8, and t adc. dynamic odt is only applicable during write cycles. if normal odt (r tt,nom ) is disa- bled, dynamic odt (r tt(wr) ) is still permitted. r tt,nom and r tt(wr) can be used inde- pendent of one another. dynamic odt is not available during write leveling mode, re- gardless of the state of odt (r tt,nom ). for details on dynamic odt operation, refer to on-die termination (odt) (page 185). 2gb: x4, x8, x16 ddr3 sdram mode register 2 (mr2) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 139 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
mode register 3 (mr3) the mode register 3 (mr3) controls additional features and functions not available in the other mode registers. currently defined is the multipurpose register (mpr). this function is controlled via the bits shown in the figure below. the mr3 is program- med via the load mode command and retains the stored information until it is pro- grammed again or until the device loses power. reprogramming the mr3 register will not alter the contents of the memory array, provided it is reprogrammed correctly. the mr3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time t mrd and t mod before initiating a sub- sequent operation. figure 52: mode register 3 (mr3) definition a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 3 (mr3) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 15 a13 a14 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mpr 1 1 ba2 16 17 0 1 0 1 0 1 0 1 0 1 m2 0 1 mpr enable normal dram operations 2 dataflow from mpr mpr_rf m15 0 1 0 1 m16 0 0 1 1 mode register mode register set (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) mpr read function predefined pattern 3 reserved reserved reserved m0 0 1 0 1 m1 0 0 1 1 notes: 1. mr3[17 and 14:3] are reserved for future use and must all be programmed to 0. 2. when mpr control is set for normal dram operation, mr3[1, 0] will be ignored. 3. intended to be used for read synchronization. multipurpose register (mpr) the multipurpose register (mpr) function is used to output a predefined system timing calibration bit sequence. bit 2 is the master bit that enables or disables access to the mpr register, and bits 1 and 0 determine which mode the mpr is placed in. the ba- sic concept of the multipurpose register is shown in figure 53 (page 141). if mr3[2] = 0, then mpr access is disabled, and the dram operates in normal mode. however, if mr3[2] = 1, then the dram no longer outputs normal read data but outputs mpr data as defined by mr3[0, 1]. if mr3[0, 1] = 00, then a predefined read pattern for system calibration is selected. to enable the mpr, the mrs command is issued to mr3, and mr3[2] = 1. prior to issu- ing the mrs command, all banks must be in the idle state (all banks are precharged, and t rp is met). when the mpr is enabled, any subsequent read or rdap commands are redirected to the multipurpose register. the resulting operation when a read or rdap command is issued, is defined by mr3[1:0] when the mpr is enabled (see ta- ble 73 (page 142)). when the mpr is enabled, only read or rdap commands are al- lowed until a subsequent mrs command is issued with the mpr disabled (mr3[2] = 0). power-down mode, self refresh, and any other non-read/rdap commands are not al- lowed during mpr enable mode. the reset function is supported during mpr enable mode. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 140 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 53: mpr block diagram memory core mr3[2] = 0 (mpr off) dq, dm, dqs, dqs# multipurpose register predefined data for reads mr3[2] = 1 (mpr on) notes: 1. a predefined data pattern can be read out of the mpr with an external read com- mand. 2. mr3[2] defines whether the data flow comes from the memory core or the mpr. when the data flow is defined, the mpr contents can be read out continuously with a regular read or rdap command. table 72: mpr functional description of mr3 bits mr3[2] mr3[1:0] function mpr mpr read function 0 dont care normal operation, no mpr transaction all subsequent reads come from the dram memory array all subsequent writes go to the dram memory array 1 a[1:0] (see table 73 (page 142)) enable mpr mode, subsequent read/rdap commands defined by bits 1 and 2 mpr functional description the jedec mpr definition enables either a prime dq (dq0 on x4 and x8; on x16, dq0 = lower byte and dq8 = upper byte) to output the mpr data with the remaining dq driv- en low, or all dq to output the mpr data. the mpr readout supports fixed read burst and read burst chop (mrs and otf via a12/bc#) with regular read latencies and ac timings applicable, provided the dll is locked as required. mpr addressing for a valid mpr read is as follows: ? a[1:0] must be set to 00 as the burst order is fixed per nibble. ? a2 selects the burst order: bl8, a2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7. ? for burst chop 4 cases, the burst order is switched on the nibble base along with the following: C a2 = 0; burst order = 0, 1, 2, 3 C a2 = 1; burst order = 4, 5, 6, 7 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 141 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
? burst order bit 0 (the first bit) is assigned to lsb, and burst order bit 7 (the last bit) is assigned to msb. ? a[9:3] are dont care. ? a10 is dont care. ? a11 is dont care. ? a12: selects burst chop mode on-the-fly, if enabled within mr0. ? a13 is a dont care ? ba[2:0] are dont care. mpr address definitions and bursting order the mpr currently supports a single data format. this data format is a predefined read pattern for system calibration. the predefined pattern is always a repeating 01 bit pat- tern. examples of the different types of predefined read pattern bursts are shown in the fol- lowing figures. table 73: mpr readouts and burst order bit mapping mr3[2] mr3[1:0] function burst length read a[2:0] burst order and data pattern 1 00 read predefined pattern for system calibration bl8 000 burst order: 0, 1, 2, 3, 4, 5, 6, 7 predefined pattern: 01010101 bc4 000 burst order: 0, 1, 2, 3 predefined pattern: 0101 bc4 100 burst order: 4, 5, 6, 7 predefined pattern: 0101 1 01 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 10 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 11 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a note: 1. burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selec- ted mpr agent. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 142 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 54: mpr system read calibration with bl8: fixed burst order single readout t0 ta0 tb0 tb1 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 ck ck# mrs prea read 1 nop nop nop nop nop nop nop nop mrs nop nop valid command t mprr dont care indicates break in time scale dqs, dqs# bank address 3 valid 3 0 a[1:0] valid 0 2 1 a2 0 2 0 00 a[9:3] valid 00 0 1 a10/ap valid 0 0 a11 valid 0 0 a12/bc# valid 1 0 0 a[15:13] valid 0 dq t mod t rp t mod rl notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 143 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 55: mpr system read calibration with bl8: fixed burst order, back-to-back readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 td ck ck# t mprr dont care indicates break in time scale rl 3 valid 3 bank address valid a[1:0] valid 0 2 0 2 0 a2 1 2 0 2 1 0 0 a[15:13] valid valid 0 a[9:3] valid valid 00 00 a11 valid valid 0 0 a12/bc# valid 1 0 0 a10/ap valid valid 0 0 1 rl prea read 1 nop nop nop nop nop nop nop nop nop mrs valid command read 1 mrs dq valid dqs, dqs# t rp t mod t ccd t mod notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 144 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 56: mpr system read calibration with bc4: lower nibble, then upper nibble t0 ta tb ck ck# dq dqs, dqs# t mod t mprr dont care tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 td nop nop nop nop nop mrs nop nop valid command mrs prea read 1 read 1 nop nop indicates break in time scale bank address 3 valid 3 valid 0 a[1:0] valid 0 2 0 2 1 a2 1 4 0 3 0 00 a[9:3] valid valid 00 0 1 a10/ap valid valid 0 0 a11 valid valid 0 0 a12/bc# valid 1 valid 1 0 0 a[15:13] valid valid 0 rl rl t rf t mod t ccd notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 0 selects lower 4 nibble bits 0 . . . 3. 4. a2 = 1 selects upper 4 nibble bits 4 . . . 7. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 145 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 57: mpr system read calibration with bc4: upper nibble, then lower nibble t0 ta tb 0 1 a10/ap valid valid 0 ck ck# mrs prea read 1 read 1 nop nop nop nop nop nop nop mrs nop nop valid command 0 0 4 1 3 1 a2 t mod t mprr 3 valid 3 bank address valid 0 2 0 2 0 a[1:0] valid 0 0 a[15:13] valid valid 0 0 a11 valid valid 00 00 a[9:3] valid valid dont care tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 td indicates break in time scale rl dq dqs, dqs# 0 a12/bc# valid 1 valid 1 0 rl t rf t mod t ccd notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 1 selects upper 4 nibble bits 4 . . . 7. 4. a2 = 0 selects lower 4 nibble bits 0 . . . 3. 2gb: x4, x8, x16 ddr3 sdram mode register 3 (mr3) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 146 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
mpr read predefined pattern the predefined read calibration pattern is a fixed pattern of 01010101. the following is an example of using the predetermined read calibration pattern. the example is to per- form multiple reads from the mpr to do system-level read timing calibration based on the predefined standard pattern. the following protocol outlines the steps used to perform the read calibration: 1. precharge all banks. 2. after t rp is satisfied, set mrs, mr3[2] = 1 and mr3[1:0] = 00. this redirects all sub- sequent reads and loads the predefined pattern into the mpr. as soon as t mrd and t mod are satisfied, the mpr is available. 3. data write operations are not allowed until the mpr returns to the normal dram state. 4. issue a read with burst order information (all other address pins are dont care): ? a[1:0] = 00 (data burst order is fixed starting at nibble) ? a2 = 0 (for bl8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) ? a12 = 1 (use bl8) 5. after rl = al + cl, the dram bursts out the predefined read calibration pattern (01010101). 6. the memory controller repeats the calibration reads until read data capture at memory controller is optimized. 7. after the last mpr read burst and after t mprr has been satisfied, issue mrs, mr3[2] = 0, and mr3[1:0] = dont care to the normal dram state. all subse- quent read and write accesses will be regular reads and writes from/to the dram array. 8. when t mrd and t mod are satisfied from the last mrs, the regular dram com- mands (such as activating a memory bank for regular read or write access) are per- mitted. mode register set (mrs) command the mode registers are loaded via inputs ba[2:0], a[13:0]. ba[2:0] determine which mode register is programmed: ? ba2 = 0, ba1 = 0, ba0 = 0 for mr0 ? ba2 = 0, ba1 = 0, ba0 = 1 for mr1 ? ba2 = 0, ba1 = 1, ba0 = 0 for mr2 ? ba2 = 0, ba1 = 1, ba0 = 1 for mr3 the mrs command can only be issued (or re-issued) when all banks are idle and in the precharged state ( t rp is satisfied and no data bursts are in progress). the controller must wait the specified time t mrd before initiating a subsequent operation such as an activate command (see figure 44 (page 128)). there is also a restriction after issuing an mrs command with regard to when the updated functions become available. this parameter is specified by t mod. both t mrd and t mod parameters are shown in fig- ure 44 (page 128) and figure 45 (page 129). violating either of these requirements will result in unspecified operation. 2gb: x4, x8, x16 ddr3 sdram mode register set (mrs) command pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 147 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
zq calibration operation the zq calibration command is used to calibrate the dram output drivers (r on ) and odt values (r tt ) over process, voltage, and temperature, provided a dedicated 240 (1%) external resistor is connected from the drams zq ball to v ssq . ddr3 sdram require a longer time to calibrate r on and odt at power-up initialization and self refresh exit, and a relatively shorter time to perform periodic calibrations. ddr3 sdram defines two zq calibration commands: zqcl and zqcs. an example of zq calibration timing is shown below. all banks must be precharged and t rp must be met before zqcl or zqcs commands can be issued to the dram. no other activities (other than issuing another zqcl or zqcs command) can be performed on the dram channel by the controller for the du- ration of t zqinit or t zqoper. the quiet time on the dram channel helps accurately cali- brate r on and odt. after dram calibration is achieved, the dram should disable the zq balls current consumption path to reduce power. zq calibration commands can be issued in parallel to dll reset and locking time. upon self refresh exit, an explicit zqcl is required if zq calibration is desired. in dual-rank systems that share the zq resistor between devices, the controller must not enable overlap of t zqinit, t zqoper, or t zqcs between ranks. figure 58: zq calibration timing (zqcl and zqcs) nop zqcl nop nop valid valid zqcs nop nop nop valid command indicates break in time scale t0 t1 ta0 ta1 ta2 ta3 tb0 tb1 tc0 tc1 tc2 address valid valid valid a10 valid valid valid ck ck# dont care dq high-z high-z 3 3 activities activ- ities valid valid odt 2 2 valid 1 cke 1 valid valid valid t zqcs t zqinit or t zqoper notes: 1. cke must be continuously registered high during the calibration procedure. 2. odt must be disabled via the odt signal or the mrs during the calibration procedure. 3. all devices connected to the dq bus should be high-z during calibration. 2gb: x4, x8, x16 ddr3 sdram zq calibration operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 148 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
activate operation before any read or write commands can be issued to a bank within the dram, a row in that bank must be opened (activated). this is accomplished via the activate com- mand, which selects both the bank and the row to be activated. after a row is opened with an activate command, a read or write command may be issued to that row, subject to the t rcd specification. however, if the additive latency is programmed correctly, a read or write command may be issued prior to t rcd (min). in this operation, the dram enables a read or write command to be issued after the activate command for that bank, but prior to t rcd (min) with the require- ment that (activate-to-read/write) + al t rcd (min) (see posted cas additive latency). t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the activate command on which a read or write command can be entered. the same procedure is used to con- vert other specification limits from time units to clock cycles. when at least one bank is open, any read-to-read command delay or write-to- write command delay is restricted to t ccd (min). a subsequent activate command to a different row in the same bank can only be is- sued after the previous active row has been closed (precharged). the minimum time in- terval between successive activate commands to the same bank is defined by t rc. a subsequent activate command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the mini- mum time interval between successive activate commands to different banks is de- fined by t rrd. no more than four bank activate commands may be issued in a given t faw (min) period, and the t rrd (min) restriction still applies. the t faw (min) param- eter applies, regardless of the number of banks already opened or closed. figure 59: example: meeting t rrd (min) and t rcd (min) command dont care t1 t0 t2 t3 t4 t5 t8 t9 t rrd row row col bank x bank y bank y nop act nop nop act nop nop rd/wr t rcd ba[2:0] ck# address ck t10 t11 nop nop indicates break in time scale 2gb: x4, x8, x16 ddr3 sdram activate operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 149 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 60: example: t faw command dont care t1 t0 t4 t5 t8 t9 t10 t11 t rrd row row bank a bank b row bank c row bank d bank y row bank y nop act nop act act nop nop t faw ba[2:0] ck# address ck t19 t20 nop act act bank e indicates break in time scale 2gb: x4, x8, x16 ddr3 sdram activate operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 150 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read operation read bursts are initiated with a read command. the starting column and bank ad- dresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. if auto precharge is disabled, the row will be left open after the completion of the burst. during read bursts, the valid data-out element from the starting column address is available read latency (rl) clocks later. rl is defined as the sum of posted cas additive latency (al) and cas latency (cl) (rl = al + cl). the value of al and cl is programma- ble in the mode register via the mrs command. each subsequent data-out element is valid nominally at the next positive or negative clock edge (that is, at the next crossing of ck and ck#). figure 61 shows an example of rl based on a cl setting of 8 and an al setting of 0. figure 61: read latency ck ck# command read nop nop nop nop nop nop nop address bank a, col n cl = 8, al = 0 dq dqs, dqs# do n t0 t7 t8 t9 t10 t11 dont care transitioning data t12 t12 indicates break in time scale notes: 1. do n = data-out from column n . 2. subsequent elements of data-out appear in the programmed order following do n . dqs, dqs# is driven by the dram along with the output data. the initial low state on dqs and high state on dqs# is known as the read preamble ( t rpre). the low state on dqs and the high state on dqs#, coincident with the last data-out element, is known as the read postamble ( t rpst). upon completion of a burst, assuming no other commands have been initiated, the dq goes high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window are de- picted in figure 72 (page 159). a detailed explanation of t dqsck (dqs transition skew to ck) is also depicted in figure 72 (page 159). data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a completed burst. the new read command should be issued t ccd cycles after the first read command. this is shown for bl8 in figure 62 (page 153). if bc4 is enabled, t ccd must still be met, which will cause a gap in the data output, as shown in figure 63 (page 153). nonconsecutive read data is reflected in 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 151 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 64 (page 154). ddr3 sdram does not allow interrupting or truncating any read burst. data from any read burst must be completed before a subsequent write burst is al- lowed. an example of a read burst followed by a write burst for bl8 is shown in fig- ure 65 (page 154) (bc4 is shown in figure 66 (page 155)). to ensure the read data is completed before the write data is on the bus, the minimum read-to-write timing is rl + t ccd - wl + 2 t ck. a read burst may be followed by a precharge command to the same bank, provided auto precharge is not activated. the minimum read-to-precharge command spac- ing to the same bank is four clocks and must also satisfy a minimum analog time from the read command. this time is called t rtp (read-to-precharge). t rtp starts al cycles later than the read command. examples for bl8 are shown in figure 67 (page 155) and bc4 in figure 68 (page 156). following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. the pre- charge command followed by another precharge command to the same bank is al- lowed. however, the precharge period will be determined by the last precharge com- mand issued to the bank. if a10 is high when a read command is issued, the read with auto precharge func- tion is engaged. the dram starts an auto precharge operation on the rising edge, which is al + t rtp cycles after the read command. dram support a t ras lockout feature (see figure 70 (page 156)). if t ras (min) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the starting point of the auto precharge operation is delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp, t rp starts at the point at which the internal precharge happens (not at the next rising clock edge after this event). the time from read with auto precharge to the next activate command to the same bank is al + ( t rtp + t rp)*, where * means rounded up to the next integer. in any event, internal precharge does not start earlier than four clocks after the last 8 n -bit prefetch. 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 152 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 62: consecutive read bursts (bl8) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 dont care transitioning data t12 t13 t14 t rpst nop read read nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# bank, col n bank, col b address 2 rl = 5 t rpre t ccd rl = 5 do n + 3 do n + 2 do n + 1 do n do n + 7 do n + 6 do n + 5 do n + 4 do b + 3 do b + 2 do b + 1 do b do b + 7 do b + 6 do b + 5 do b + 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0 and t4. 3. do n (or b ) = data-out from column n (or column b ). 4. bl8, rl = 5 (cl = 5, al = 0). figure 63: consecutive read bursts (bc4) nop ck ck# command 1 dq 3 dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 address 2 t10 t11 dont care transitioning data t12 t13 t14 read read nop nop nop nop nop nop nop nop nop nop nop nop bank, col n bank, col b t rpst t rpre t rpst t rpre rl = 5 do n + 3 do n + 2 do n + 1 do n do b + 3 do b + 2 do b + 1 do b rl = 5 t ccd notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 setting is activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during read command at t0 and t4. 3. do n (or b ) = data-out from column n (or column b ). 4. bc4, rl = 5 (cl = 5, al = 0). 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 153 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 64: nonconsecutive read bursts dont care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 dqs, dqs# command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read nop read address bank a, col n bank a, col b ck ck# dq do n do b cl = 8 cl = 8 notes: 1. al = 0, rl = 8. 2. do n (or b ) = data-out from column n (or column b ). 3. seven subsequent elements of data-out appear in the programmed order following do n . 4. seven subsequent elements of data-out appear in the programmed order following do b . figure 65: read (bl8) to write (bl8) dont care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck# command 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wpst t rpre t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write command delay = rl + t ccd + 2 t ck - wl t bl = 4 clocks address 2 bank, col b bank, col n rl = 5 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. 3. do n = data-out from column, di b = data-in for column b . 4. bl8, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 154 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 66: read (bc4) to write (bc4) otf dont care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck# address 2 command 1 t wpst t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wtr t bl = 4 clocks t rpre rl = 5 read-to-write command delay = rl + t ccd/2 + 2 t ck - wl read do n do n + 1 do n + 2 do n + 3 di n di n + 1 di n + 2 di n + 3 bank, col b bank, col n nop nop nop write nop nop nop nop nop nop nop nop nop nop nop notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 otf setting is activated by mr0[1:0] and a12 = 0 during read command at t0 and write command at t4. 3. do n = data-out from column n ; di n = data-in from column b . 4. bc4, rl = 5 (al - 0, cl = 5), wl = 5 (al = 0, cwl = 5). figure 67: read to precharge (bl8) t ras t rtp ck ck# command nop nop nop nop address dq dqs, dqs# dont care transitioning data nop nop nop nop nop act nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 nop read bank a, col n nop pre bank a, (or all) bank a, row b t rp do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 155 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 68: read to precharge (bc4) ck ck# dont care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 command nop nop nop nop nop nop nop nop nop act nop nop nop nop nop read nop pre address bank a, col n bank a, (or all) bank a, row b t rp t rtp dqs, dqs# dq do n do n + 1 do n + 2 do n + 3 t ras figure 69: read to precharge (al = 5, cl = 6) ck ck# command nop nop nop nop address dq dqs, dqs# dont care transitioning data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 nop read bank a, col n nop pre bank a, (or all) act bank a, row b nop nop t ras cl = 6 al = 5 t rtp t rp do n + 3 do n + 2 do n do n + 1 figure 70: read with auto precharge (al = 4, cl = 6) ck ck# command nop nop nop nop address dq dqs, dqs# dont care transitioning data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ta0 t rtp (min) nop read nop al = 4 nop nop cl = 6 nop t ras (min) act indicates break in time scale t rp bank a, col n bank a, row b do n do n + 1 do n + 2 do n + 3 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 156 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
dqs to dq output timing is shown in figure 71 (page 158). the dq transitions between valid data outputs must be within t dqsq of the crossing point of dqs, dqs#. dqs must also maintain a minimum high and low time of t qsh and t qsl. prior to the read preamble, the dq balls will either be floating or terminated, depending on the status of the odt signal. figure 72 (page 159) shows the strobe-to-clock timing during a read. the crossing point dqs, dqs# must transition within t dqsck of the clock crossing point. the data out has no timing relationship to ck, only to dqs, as shown in figure 72 (page 159). figure 72 (page 159) also shows the read preamble and postamble. typically, both dqs and dqs# are high-z to save power (v ddq ). prior to data output from the dram, dqs is driven low and dqs# is high for t rpre. this is known as the read preamble. the read postamble, t rpst, is one half clock from the last dqs, dqs# transition. dur- ing the read postamble, dqs is driven low and dqs# is high. when complete, the dq is disabled or continues terminating, depending on the state of the odt signal. fig- ure 77 (page 163) demonstrates how to measure t rpst. 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 157 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 71: data output timing C t dqsq and data valid window t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, col n t rpst nop read nop nop nop nop nop nop nop nop nop ck ck# command 1 address 2 t dqsq (max) dqs, dqs# dq 3 (last data valid) dq 3 (first data no longer valid) all dq collectively do n do n + 3 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 3 do n + 2 do n + 1 do n do n + 7 do n + 6 do n + 5 do n do n + 3 t rpre dont care data valid data valid t qh t qh t hz dq (max) do n + 4 rl = al + cl t dqsq (max) t lz dq (min) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1, 0] = 0, 0 or mr0[0, 1] = 0, 1 and a12 = 1 during read command at t0. 3. do n = data-out from column n . 4. bl8, rl = 5 (al = 0, cl = 5). 5. output timings are referenced to v ddq /2 and dll on and locked. 6. t dqsq defines the skew between dqs, dqs# to data and does not define dqs, dqs# to ck. 7. early data transitions may not always happen at the same dq. data transitions of a dq can be early or late within a burst. 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 158 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level that specifies when the device out- put is no longer driving t hzdqs and t hzdq, or begins driving t lzdqs, t lzdq. fig- ure 73 (page 160) shows a method of calculating the point when the device is no longer driving t hzdqs and t hzdq, or begins driving t lzdqs, t lzdq, by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters t lzdqs, t lzdq, t hzdqs, and t hzdq are defined as single-ended. figure 72: data strobe timing C reads rl measured to this point dqs, dqs# early strobe ck t lzdqs (min) t hzdqs (min) dqs, dqs# late strobe t lzdqs (max) t hzdqs (max) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (min) t dqsck (min) t dqsck (min) t dqsck (min) ck# t rpre t qsh t qsh t qsl t qsl t qsl t qsl t qsh t qsh bit 0 bit 1 bit 2 bit 7 t rpre bit 0 bit 1 bit 2 bit 7 bit 6 bit 3 bit 4 bit 5 bit 6 bit 4 bit 3 bit 5 t rpst t rpst t0 t1 t2 t3 t4 t5 t6 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 159 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 73: method for calculating t lz and t hz t hzdqs, t hzdq t hzdqs, t hzdq end point = 2 t1 - t2 v oh - xmv v tt - xmv v ol + xmv v tt + xmv v oh - 2xmv v tt - 2xmv v ol + 2xmv v tt + 2xmv t lzdqs, t lzdq t lzdqs, t lzdq begin point = 2 t1 - t2 t1 t1 t2 t2 notes: 1. within a burst, the rising strobe edge is not necessarily fixed at t dqsck (min) or t dqsck (max). instead, the rising strobe edge can vary between t dqsck (min) and t dqsck (max). 2. the dqs high pulse width is defined by t qsh, and the dqs low pulse width is defined by t qsl. likewise, t lzdqs (min) and t hzdqs (min) are not tied to t dqsck (min) (early strobe case), and t lzdqs (max) and t hzdqs (max) are not tied to t dqsck (max) (late strobe case); however, they tend to track one another. 3. the minimum pulse width of the read preamble is defined by t rpre (min). the mini- mum pulse width of the read postamble is defined by t rpst (min). figure 74: t rpre timing t rpre dqs - dqs# dqs dqs# t1 t rpre begins t2 t rpre ends ck ck# v tt resulting differential signal relevant for t rpre specification t c t a t b t d single-ended signal provided as background information 0v single-ended signal provided as background information v tt v tt 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 160 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 75: t rpst timing t rpst dqs - dqs# dqs dqs# t1 t rpst begins t2 t rpst ends resulting differential signal relevant for t rpst specification ck ck# v tt t c t a t b t d single-ended signal, provided as background information single-ended signal, provided as background information 0v v tt v tt 2gb: x4, x8, x16 ddr3 sdram read operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 161 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
write operation write bursts are initiated with a write command. the starting column and bank ad- dresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is selected, the row being accessed is pre- charged at the end of the write burst. if auto precharge is not selected, the row will remain open for subsequent accesses. after a write command has been issued, the write burst may not be interrupted. for the generic write commands used in fig- ure 78 (page 164) through figure 86 (page 169), auto precharge is disabled. during write bursts, the first valid data-in element is registered on a rising edge of dqs following the write latency (wl) clocks later and subsequent data elements will be registered on successive edges of dqs. write latency (wl) is defined as the sum of posted cas additive latency (al) and cas write latency (cwl): wl = al + cwl. the values of al and cwl are programmed in the mr0 and mr2 registers, respectively. prior to the first valid dqs edge, a full cycle is needed (including a dummy crossover of dqs, dqs#) and specified as the write preamble shown in figure 78 (page 164). the half cycle on dqs following the last data-in element is known as the write postamble. the time between the write command and the first valid edge of dqs is wl clocks t dqss. figure 79 (page 165) through figure 86 (page 169) show the nominal case where t dqss = 0ns; however, figure 78 (page 164) includes t dqss (min) and t dqss (max) cases. data may be masked from completing a write using data mask. the data mask occurs on the dm ball aligned to the write data. if dm is low, the write completes normal- ly. if dm is high, that bit of data is masked. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z, and any additional input data will be ignored. data for any write burst may be concatenated with a subsequent write command to provide a continuous flow of input data. the new write command can be t ccd clocks following the previous write command. the first data element from the new burst is applied after the last element of a completed burst. figure 79 (page 165) and figure 80 (page 165) show concatenated bursts. an example of nonconsecutive writes is shown in figure 81 (page 166). data for any write burst may be followed by a subsequent read command after t wtr has been met (see figure 82 (page 166), figure 83 (page 167), and figure 84 (page 168)). data for any write burst may be followed by a subsequent precharge command, providing t wr has been met, as shown in figure 85 (page 169) and figure 86 (page 169). both t wtr and t wr starting time may vary, depending on the mode register settings (fixed bc4, bl8 versus otf). 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 162 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 76: t wpre timing dqs - dqs# t1 t wpre begins t2 t wpre ends t wpre resulting differential signal relevant for t wpre specification 0v ck ck# v tt figure 77: t wpst timing t wpst dqs - dqs# t1 t wpst begins t2 t wpst ends resulting differential signal relevant for t wpst specification 0v ck ck# v tt 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 163 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 78: write burst di n + 3 di n + 2 di n + 1 di n t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 dont care transitioning data di n + 7 di n + 6 di n + 5 di n + 4 bank, col n nop write nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# address 2 t wpst t wpre t wpst t dqsl dq 3 dq 3 t wpst dqs, dqs# dqs, dqs# t dqsl t wpre t dqss t dqss t dsh t dsh t dsh t dsh t dss t dss t dss t dss t dss t dss t dss t dss t dss t dss t dsh t dsh t dsh t dsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsl t dqsl t dqsl t dqsh t dqsh t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh wl = al + cwl t dqss (min) t dqss (nom) t dqss (max) t dqsl t wpre di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write command at t0. 3. di n = data-in for column n . 4. bl8, wl = 5 (al = 0, cwl = 5). 5. t dqss must be met at each rising clock edge. 6. t wpst is usually depicted as ending at the crossing of dqs, dqs#; however, t wpst ac- tually ends when dqs no longer drives low and dqs# no longer drives high. 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 164 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 79: consecutive write (bl8) to write (bl8) wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 dont care transitioning data t12 t13 t14 valid valid nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# address 2 t wpst t wr t wtr t bl = 4 clocks di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write commands at t0 and t4. 3. di n (or b ) = data-in for column n (or column b ). 4. bl8, wl = 5 (al = 0, cwl = 5). figure 80: consecutive write (bc4) to write (bc4) via otf wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 dont care transitioning data t12 t13 t14 valid valid nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# address 2 t wpst t wr t wtr t wpst t wpre di n + 3 di n + 2 di n + 1 di n di b + 3 di b + 2 di b + 1 di b t bl = 4 clocks notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bc4, wl = 5 (al = 0, cwl = 5). 3. di n (or b ) = data-in for column n (or column b ). 4. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0 and t4. 5. if set via mrs (fixed) t wr and t wtr would start t11 (2 cycles earlier). 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 165 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 81: nonconsecutive write to write ck ck# command nop nop nop address dq dm dqs, dqs# transitioning data nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 nop write nop write valid valid nop di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 don't care di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 wl = cwl + al = 7 wl = cwl + al = 7 notes: 1. di n (or b ) = data-in for column n (or column b ). 2. seven subsequent elements of data-in are applied in the programmed order following do n . 3. each write command may be to any bank. 4. shown for wl = 7 (cwl = 7, al = 0). figure 82: write (bl8) to read (bl8) wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 dont care transitioning data ta0 nop write read valid valid nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# address 3 t wpst t wtr 2 indicates break in time scale di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t9. 3. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and mr0[12] = 1 during the write command at t0. the read command at ta0 can be either bc4 or bl8, depending on mr0[1:0] and the a12 status at ta0. 4. di n = data-in for column n . 5. rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 166 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 83: write to read (bc4 mode register setting) wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 dont care transitioning data nop write valid read valid nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# address 3 t wpst t wtr 2 t wpre indicates break in time scale di n + 3 di n + 2 di n + 1 di n notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. 3. the fixed bc4 setting is activated by mr0[1:0] = 10 during the write command at t0 and the read command at ta0. 4. di n = data-in for column n . 5. bc4 (fixed), wl = 5 (al = 0, cwl = 5), rl = 5 (al = 0, cl = 5). 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 167 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 84: write (bc4 otf) to read (bc4 otf) wl = 5 rl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 dont care transitioning data tn nop write read valid valid nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# address 3 t wpst t bl = 4 clocks nop t wtr 2 indicates break in time scale di n + 3 di n + 2 di n + 1 di n notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts after t bl. 3. the bc4 otf setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0 and the read command at t n . 4. di n = data-in for column n . 5. bc4, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 168 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 85: write (bl8) to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 nop write valid nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck# command dq bl8 dqs, dqs# address dont care transitioning data indicates break in time scale t wr wl = al + cwl valid notes: 1. di n = data-in from column n . 2. seven subsequent elements of data-in are applied in the programmed order following do n . 3. shown for wl = 7 (al = 0, cwl = 7). figure 86: write (bc4 mode register setting) to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n nop write valid nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck# command dq bc4 dqs, dqs# address dont care transitioning data indicates break in time scale t wr wl = al + cwl valid notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data is shown at t7. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 3. the fixed bc4 setting is activated by mr0[1:0] = 10 during the write command at t0. 4. di n = data-in for column n . 5. bc4 (fixed), wl = 5, rl = 5. 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 169 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 87: write (bc4 otf) to precharge wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tn dont care transitioning data bank, col n nop write pre nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# address 3 t wpst t wpre indicates break in time scale di n + 3 di n + 2 di n + 1 di n t wr 2 valid notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the rising clock edge at t9. t wr speci- fies the last burst write cycle until the precharge command can be issued to the same bank. 3. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0. 4. di n = data-in for column n . 5. bc4 (otf), wl = 5, rl = 5. dq input timing figure 78 (page 164) shows the strobe-to-clock timing during a write burst. dqs, dqs# must transition within 0.25 t ck of the clock transitions, as limited by t dqss. all data and data mask setup and hold timings are measured relative to the dqs, dqs# crossing, not the clock crossing. the write preamble and postamble are also shown in figure 78 (page 164). one clock prior to data input to the dram, dqs must be high and dqs# must be low. then for a half clock, dqs is driven low (dqs# is driven high) during the write preamble, t wpre. likewise, dqs must be kept low by the controller after the last data is written to the dram during the write postamble, t wpst. data setup and hold times are also shown in figure 78 (page 164). all setup and hold times are measured from the crossing points of dqs and dqs#. these setup and hold values pertain to data input and data mask input. additionally, the half period of the data input strobe is specified by t dqsh and t dqsl. 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 170 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 88: data input timing t dh t dh t ds t ds dm dq di b dqs, dqs# dont care transitioning data t dqsh t dqsl t wpre t wpst 2gb: x4, x8, x16 ddr3 sdram write operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 171 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
precharge operation input a10 determines whether one bank or all banks are to be precharged and, in the case where only one bank is to be precharged, inputs ba[2:0] select the bank. when all banks are to be precharged, inputs ba[2:0] are treated as dont care. after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued. self refresh operation the self refresh operation is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. all power supply inputs (including v refca and v refdq ) must be maintained at valid lev- els upon entry/exit and during self refresh mode operation. v refdq may float or not drive v ddq /2 while in self refresh mode under certain conditions: ?v ss < v refdq < v dd is maintained. ?v refdq is valid and stable prior to cke going back high. ? the first write operation may not occur earlier than 512 clocks after v refdq is valid. ? all other self refresh mode exit timing requirements are met. the dram must be idle with all banks in the precharge state ( t rp is satisfied and no bursts are in progress) before a self refresh entry command can be issued. odt must also be turned off before self refresh entry by registering the odt ball low prior to the self refresh entry command (see on-die termination (odt) (page 185) for timing re- quirements). if r tt,nom and r tt(wr) are disabled in the mode registers, odt can be a dont care. after the self refresh entry command is registered, cke must be held low to keep the dram in self refresh mode. after the dram has entered self refresh mode, all external control signals, except cke and reset#, are dont care. the dram initiates a minimum of one refresh com- mand internally within the t cke period when it enters self refresh mode. the requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. first and foremost, the clock must be stable (meeting t ck specifications) when self refresh mode is entered. if the clock remains stable and the frequency is not altered while in self refresh mode, then the dram is allowed to exit self refresh mode after t ckesr is satisfied (cke is allowed to transition high t ckesr later than when cke was registered low). since the clock remains stable in self refresh mode (no frequency change), t cksre and t cksrx are not required. however, if the clock is altered during self refresh mode (if it is turned-off or its frequency changes), then t cksre and t cksrx must be satisfied. when entering self refresh mode, t cksre must be satisfied prior to altering the clock's frequency. prior to exiting self refresh mode, t cksrx must be satisfied prior to registering cke high. when cke is high during self refresh exit, nop or des must be issued for t xs time. t xs is required for the completion of any internal refresh already in progress and must be satisfied before a valid command not requiring a locked dll can be issued to the de- vice. t xs is also the earliest time self refresh re-entry may occur. before a command re- quiring a locked dll can be applied, a zqcl command must be issued, t zqoper tim- ing must be met, and t xsdll must be satisfied. odt must be off during t xsdll. 2gb: x4, x8, x16 ddr3 sdram precharge operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 172 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 89: self refresh entry/exit timing ck ck# command nop nop 4 sre (ref) 3 address cke odt 2 reset# 2 valid valid 6 srx (nop) nop 5 t rp 8 t xsdll 7, 9 odtl t is t cpded t is t is enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 t2 tc0 tc1 td0 tb0 dont care te0 valid valid 7 valid valid valid t ih ta0 tf0 indicates break in time scale t cksrx 1 t cksre 1 t xs 6, 9 t ckesr (min) 1 notes: 1. the clock must be valid and stable, meeting t ck specifications at least t cksre after en- tering self refresh mode, and at least t cksrx prior to exiting self refresh mode, if the clock is stopped or altered between states ta0 and tb0. if the clock remains valid and unchanged from entry and during self refresh mode, then t cksre and t cksrx do not apply; however, t ckesr must be satisfied prior to exiting at srx. 2. odt must be disabled and r tt off prior to entering self refresh at state t1. if both r tt,nom and r tt(wr) are disabled in the mode registers, odt can be a dont care. 3. self refresh entry (sre) is synchronous via a refresh command with cke low. 4. a nop or des command is required at t2 after the sre command is issued prior to the inputs becoming dont care. 5. nop or des commands are required prior to exiting self refresh mode until state te0. 6. t xs is required before any commands not requiring a locked dll. 7. t xsdll is required before any commands requiring a locked dll. 8. the device must be in the all banks idle state prior to entering self refresh mode. for example, all banks must be precharged, t rp must be met, and no data bursts can be in progress. 9. self refresh exit is asynchronous; however, t xs and t xsdll timings start at the first rising clock edge where cke high satisfies t isxr at tc1. t cksrx timing is also measured so that t isxr is satisfied at tc1. 2gb: x4, x8, x16 ddr3 sdram self refresh operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 173 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
extended temperature usage microns ddr3 sdram support the optional extended case temperature (t c ) range of 0c to 95c. thus, the srt and asr options must be used at a minimum. the extended temperature range dram must be refreshed externally at 2x (double re- fresh) anytime the case temperature is above 85c (and does not exceed 95c). the ex- ternal refresh requirement is accomplished by reducing the refresh period from 64ms to 32ms. however, self refresh mode requires either asr or srt to support the extended temperature. thus, either asr or srt must be enabled when t c is above 85c or self refresh cannot be used until t c is at or below 85c. table 74 summarizes the two exten- ded temperature options and table 75 summarizes how the two extended temperature options relate to one another. table 74: self refresh temperature and auto self refresh description field mr2 bits description self refresh temperature (srt) srt 7 if asr is disabled (mr2[6] = 0), srt must be programmed to indicate t oper during self refresh: *mr2[7] = 0: normal operating temperature range (0c to 85c) *mr2[7] = 1: extended operating temperature range (0c to 95c) if asr is enabled (mr2[7] = 1), srt must be set to 0, even if the extended temperature range is supported *mr2[7] = 0: srt is disabled auto self refresh (asr) asr 6 when asr is enabled, the dram automatically provides self refresh power management func- tions, (refresh rate for all supported operating temperature values) * mr2[6] = 1: asr is enabled (m7 must = 0) when asr is not enabled, the srt bit must be programmed to indicate t oper during self refresh operation * mr2[6] = 0: asr is disabled; must use manual self refresh temperature (srt) table 75: self refresh mode summary mr2[6] (asr) mr2[7] (srt) self refresh operation permitted operating temperature range for self refresh mode 0 0 self refresh mode is supported in the normal temperature range normal (0c to 85c) 0 1 self refresh mode is supported in normal and extended temper- ature ranges; when srt is enabled, it increases self refresh power consumption normal and extended (0c to 95c) 1 0 self refresh mode is supported in normal and extended temper- ature ranges; self refresh power consumption may be tempera- ture-dependent normal and extended (0c to 95c) 1 1 illegal 2gb: x4, x8, x16 ddr3 sdram extended temperature usage pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 174 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
power-down mode power-down is synchronously entered when cke is registered low coincident with a nop or des command. cke is not allowed to go low while an mrs, mpr, zqcal, read, or write operation is in progress. cke is allowed to go low while any of the other legal operations (such as row activation, precharge, auto precharge, or re- fresh) are in progress. however, the power-down i dd specifications are not applicable until such operations have completed. depending on the previous dram state and the command issued prior to cke going low, certain timing constraints must be satisfied (as noted in table 76). timing diagrams detailing the different power-down mode entry and exits are shown in figure 90 (page 177) through figure 99 (page 182). table 76: command to power-down entry parameters dram status last command prior to cke low 1 parameter (min) parameter value figure idle or active activate t actpden 1 t ck figure 97 (page 181) idle or active precharge t prpden 1 t ck figure 98 (page 181) active read or readap t rdpden rl + 4 t ck + 1 t ck figure 93 (page 179) active write: bl8otf, bl8mrs, bc4otf t wrpden wl + 4 t ck + t wr/ t ck figure 94 (page 179) active write: bc4mrs wl + 2 t ck + t wr/ t ck figure 94 (page 179) active writeap: bl8otf, bl8mrs, bc4otf t wrapden wl + 4 t ck + wr + 1 t ck figure 95 (page 180) active writeap: bc4mrs wl + 2 t ck + wr + 1 t ck figure 95 (page 180) idle refresh t refpden 1 t ck figure 96 (page 180) power-down refresh t xpdll greater of 10 t ck or 24ns figure 100 (page 182) idle mode register set t mrspden t mod figure 99 (page 182) note: 1. if slow-exit mode precharge power-down is enabled and entered, odt becomes asyn- chronous t anpd prior to cke going low and remains asynchronous until t anpd + t xpdll after cke goes high. entering power-down disables the input and output buffers, excluding ck, ck#, odt, cke, and reset#. nop or des commands are required until t cpded has been satis- fied, at which time all specified input/output buffers are disabled. the dll should be in a locked state when power-down is entered for the fastest power-down exit timing. if the dll is not locked during power-down entry, the dll must be reset after exiting power-down mode for proper read operation as well as synchronous odt operation. during power-down entry, if any bank remains open after all in-progress commands are complete, the dram will be in active power-down mode. if all banks are closed after all in-progress commands are complete, the dram will be in precharge power-down mode. precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. when entering precharge power-down mode, the dll is turned off in slow exit mode or kept on in fast exit mode. the dll also remains on when entering active power-down. odt has special timing constraints when slow exit mode precharge power-down is enabled and entered. refer to asynchronous odt mode (page 198) for detailed odt usage requirements in slow 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 175 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
exit mode precharge power-down. a summary of the two power-down modes is listed in table 77 (page 176). while in either power-down state, cke is held low, reset# is held high, and a stable clock signal must be maintained. odt must be in a valid state but all other input signals are dont care. if reset# goes low during power-down, the dram will switch out of power-down mode and go into the reset state. after cke is registered low, cke must remain low until t pd (min) has been satisfied. the maximum time allowed for power- down duration is t pd (max) (9 t refi). the power-down states are synchronously exited when cke is registered high (with a required nop or des command). cke must be maintained high until t cke has been satisfied. a valid, executable command may be applied after power-down exit latency, t xp, and t xpdll have been satisfied. a summary of the power-down modes is listed be- low. for specific cke-intensive operations, such as repeating a power-down-exit-to-refresh- to-power-down-entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient to keep the dll properly updated. in addi- tion to meeting t pd when the refresh command is used between power-down exit and power-down entry, two other conditions must be met. first, t xp must be satisfied before issuing the refresh command. second, t xpdll must be satisfied before the next power-down may be entered. an example is shown in figure 100 (page 182). table 77: power-down modes dram state mr1[12] dll state power- down exit relevant parameters active (any bank open) dont care on fast t xp to any other valid command precharged (all banks precharged) 1 on fast t xp to any other valid command 0 off slow t xpdll to commands that require the dll to be locked (read, rdap, or odt on); t xp to any other valid command 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 176 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 90: active power-down entry and exit ck ck# command nop nop nop nop address cke t ck t ch t cl enter power-down mode exit power-down mode dont care valid valid valid t cpded valid t is t ih t ih t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 nop t xp t cke (min) indicates break in time scale t pd 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 177 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 91: precharge power-down (fast-exit mode) entry and exit ck ck# command nop nop nop nop cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid t cpded t is t ih t is t0 t1 t2 t3 t4 t5 ta0 ta1 nop dont care indicates break in time scale t xp t cke (min) figure 92: precharge power-down (slow-exit mode) entry and exit ck ck# command nop nop nop cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid 2 valid 1 pre t xpdll t cpded t is t ih t is t0 t1 t2 t3 t4 ta ta1 tb nop dont care indicates break in time scale t xp t cke (min) notes: 1. any valid command not requiring a locked dll. 2. any valid command requiring a locked dll. 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 178 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 93: power-down entry after read or read with auto precharge (rdap) t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 dont care transitioning data ta10 ta11 ta12 nop valid read/ rdap nop nop nop nop nop nop nop nop nop ck ck# command dq bl8 dq bc4 dqs, dqs# address cke t cpded t is t pd power-down or self refresh entry indicates break in time scale t rdpden di n + 3 di n + 1 di n + 2 di n rl = al + cl di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n+ 5 di n + 4 figure 94: power-down entry after write t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb0 tb1 tb2 tb3 tb4 nop write valid nop nop nop nop nop nop nop nop nop nop nop ck ck# command dq bl8 dq bc4 dqs, dqs# address cke t cpded power-down or self refresh entry 1 dont care transitioning data t wrpden di n + 3 di n + 1 di n + 2 di n t pd indicates break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 t is wl = al + cwl t wr note: 1. cke can go low 2 t ck earlier if bc4mrs. 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 179 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 95: power-down entry after write with auto precharge (wrap) t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb0 tb1 dont care transitioning data tb2 tb3 tb4 nop wrap valid nop nop nop nop nop nop nop nop nop nop nop ck ck# command dq bl8 dq bc4 dqs, dqs# address a10 cke t pd t wrapden power-down or self refresh entry 2 start internal precharge t cpded t is indicates break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n wr 1 wl = al + cwl notes: 1. t wr is programmed through mr0[11:9] and represents t wrmin (ns)/ t ck rounded up to the next integer t ck. 2. cke can go low 2 t ck earlier if bc4mrs. figure 96: refresh to power-down entry ck ck# command refresh nop nop nop nop valid cke t ck t ch t cl t cpded t refpden t is t0 t1 t2 t3 ta0 ta1 ta2 tb0 t xp (min) t rfc (min) 1 dont care indicates break in time scale t cke (min) t pd note: 1. after cke goes high during t rfc, cke must remain high until t rfc is satisfied. 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 180 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 97: activate to power-down entry ck ck# command address active nop nop cke t ck t ch t cl dont care t cpded t actpden valid t is t0 t1 t2 t3 t4 t5 t6 t7 t pd figure 98: precharge to power-down entry ck ck# command address cke t ck t ch t cl dont care t cpded t prepden t is t0 t1 t2 t3 t4 t5 t6 t7 t pd all/single bank pre nop nop 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 181 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 99: mrs command to power-down entry ck ck# cke t ck t ch t cl t cpded address t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 t pd dont care indicates break in time scale valid command mrs nop nop nop nop nop t mrspden figure 100: power-down exit to refresh to power-down entry ck ck# cke t ck t ch t cl enter power-down mode enter power-down mode exit power-down mode t pd t cpded t is t ih t is t0 t1 t2 t3 t4 ta0 ta1 tb0 dont care indicates break in time scale command nop nop nop nop refresh nop nop t xp 1 t xpdll 2 notes: 1. t xp must be satisfied before issuing the command. 2. t xpdll must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. 2gb: x4, x8, x16 ddr3 sdram power-down mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 182 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
reset operation the reset signal (reset#) is an asynchronous reset signal that triggers any time it drops low, and there are no restrictions about when it can go low. after reset# goes low, it must remain low for 100ns. during this time, the outputs are disabled, odt (r tt ) turns off (high-z), and the dram resets itself. cke should be driven low prior to reset# being driven high. after reset# goes high, the dram must be re-initialized as though a normal power-up was executed. all refresh counters on the dram are reset, and data stored in the dram is assumed unknown after reset# has gone low. 2gb: x4, x8, x16 ddr3 sdram reset operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 183 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 101: reset sequence cke r tt ba[2:0] all voltage supplies valid and stable high-z dm dqs high-z address a10 ck ck# t cl command nop t0 ta0 dont care t cl t is odt dq high-z tb0 t dllk mr1 with dll enable mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code valid valid valid valid normal operation mr2 mr3 mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td0 reset# stable and valid clock valid valid dram ready for external commands t1 t zqinit a10 = h zqcl t is valid valid valid system reset (warm boot) zqcal mr0 with dll reset t = 10ns (min) t = 100ns (min) indicates break in time scale t = 500s (min) t xpr t mrd t mrd t mrd t mod t ck t (min) = max (10ns, 5 t ck) 1 t ioz = 20ns note: 1. the minimum time required is the longer of 10ns or 5 clocks. 2gb: x4, x8, x16 ddr3 sdram reset operation pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 184 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
on-die termination (odt) on-die termination (odt) is a feature that enables the dram to enable/disable and turn on/off termination resistance for each dq, dqs, dqs#, and dm for the x4 and x8 configurations (and tdqs, tdqs# for the x8 configuration, when enabled). odt is ap- plied to each dq, udqs, udqs#, ldqs, ldqs#, udm, and ldm signal for the x16 con- figuration. odt is designed to improve signal integrity of the memory channel by enabling the dram controller to independently turn on/off the drams internal termination resist- ance for any grouping of dram devices. odt is not supported during dll disable mode (simple functional representation shown below). the switch is enabled by the in- ternal odt control logic, which uses the external odt ball and other control informa- tion. figure 102: on-die termination odt v ddq /2 r tt switch dq, dqs, dqs#, dm, tdqs, tdqs# to other circuitry such as rcv, . . . functional representation of odt the value of r tt (odt termination resistance value) is determined by the settings of several mode register bits (see table 82 (page 188)). the odt ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers mr1 and mr2 are programmed to disable odt. odt is comprised of nominal odt and dynamic odt modes and either of these can function in synchronous or asynchronous mode (when the dll is off during precharge power-down or when the dll is synchro- nizing). nominal odt is the base termination and is used in any allowable odt state. dynamic odt is applied only during writes and provides otf switching from no r tt or r tt,nom to r tt(wr) . the actual effective termination, r tt(eff) , may be different from r tt targeted due to nonlinearity of the termination. for r tt(eff) values and calculations, see on page . nominal odt odt (nom) is the base termination resistance for each applicable ball; it is enabled or disabled via mr1[9, 6, 2] (see mode register 1 (mr1) definition), and it is turned on or off via the odt ball. 2gb: x4, x8, x16 ddr3 sdram on-die termination (odt) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 185 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 78: truth table C odt (nominal) note 1 applies to the entire table mr1[9, 6, 2] odt pin dram termination state dram state notes 000 0 r tt,nom disabled, odt off any valid 2 000 1 r tt,nom disabled, odt on any valid except self refresh, read 3 000C101 0 r tt,nom enabled, odt off any valid 2 000C101 1 r tt,nom enabled, odt on any valid except self refresh, read 3 110 and 111 x r tt,nom reserved, odt on or off illegal notes: 1. assumes dynamic odt is disabled (see dynamic odt (page 187) when enabled). 2. odt is enabled and active during most writes for proper termination, but it is not illegal for it to be off during writes. 3. odt must be disabled during reads. the r tt,nom value is restricted during writes. dynam- ic odt is applicable if enabled. nominal odt resistance r tt,nom is defined by mr1[9, 6, 2], as shown in mode register 1 (mr1) definition. the r tt,nom termination value applies to the output pins previously mentioned. ddr3 sdram supports multiple r tt,nom values based on rzq/ n where n can be 2, 4, 6, 8, or 12 and rzq is 240 . r tt,nom termination is allowed any time after the dram is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. write accesses use r tt,nom if dynamic odt (r tt(wr) ) is disabled. if r tt,nom is used dur- ing writes, only rzq/2, rzq/4, and rzq/6 are allowed (see table 82 (page 188)). odt timings are summarized in table 79 (page 186), as well as listed in table 51 (page 71). examples of nominal odt timing are shown in conjunction with the synchronous mode of operation in synchronous odt mode (page 193). table 79: odt parameters symbol description begins at defined to definition for all ddr3 speed bins unit odtlon odt synchronous turn-on delay odt registered high r tt(on) t aon cwl + al - 2 t ck odtloff odt synchronous turn-off delay odt registered high r tt(off) t aof cwl + al - 2 t ck t aonpd odt asynchronous turn-on delay odt registered high r tt(on) 2C8.5 ns t aofpd odt asynchronous turn-off delay odt registered high r tt(off) 2C8.5 ns odth4 odt minimum high time after odt assertion or write (bc4) odt registered high or write registration with odt high odt registered low 4 t ck t ck odth8 odt minimum high time after write (bl8) write registration with odt high odt registered low 6 t ck t ck t aon odt turn-on relative to odtlon completion completion of odtlon r tt(on) see table 51 (page 71) ps t aof odt turn-off relative to odtloff completion completion of odtloff r tt(off) 0.5 t ck 0.2 t ck t ck 2gb: x4, x8, x16 ddr3 sdram on-die termination (odt) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 186 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
dynamic odt in certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command, essentially changing the odt termination on the fly. with dynamic odt r tt(wr) ) enabled, the dram switches from nominal odt r tt,nom ) to dy- namic odt r tt(wr) ) when beginning a write burst and subsequently switches back to nominal odt r tt,nom ) at the completion of the write burst. this requirement is sup- ported by the dynamic odt feature, as described below. dynamic odt special use case when ddr3 devices are architect as a single rank memory array, dynamic odt offers a special use case: the odt ball can be wired high (via a current limiting resistor prefer- red) by having r tt,nom disabled via mr1 and r tt(wr) enabled via mr2. this will allow the odt signal not to have to be routed yet the dram can provide odt coverage dur- ing write accesses. when enabling this special use case, some standard odt spec conditions may be viola- ted: odt is sometimes suppose to be held low. such odt spec violation (odt not low) is allowed under this special use case. most notably, if write leveling is used, this would appear to be a problem since r tt(wr) can not be used (should be disabled) and r tt(nom) should be used. for write leveling during this special use case, with the dll locked, then r tt(nom) maybe enabled when entering write leveling mode and disabled when exiting write leveling mode. more so, r tt(nom) must be enabled when enabling write leveling, via same mr1 load, and disabled when disabling write leveling, via same mr1 load if r tt(nom) is to be used. odt will turn-on within a delay of odtlon + t aon + t mod + 1ck (enabling via mr1) or turn-off within a delay of odtloff + t aof + t mod + 1ck. as seen in the table below, between the load mode of mr1 and the previously specified delay, the value of odt is uncertain. this means the dq odt termination could turn-on and then turn-off again during the period of stated uncertainty. table 80: write leveling with dynamic odt special case begin r tt,nom uncertainty end r tt,nom uncertainty i/os r tt,nom final state mr1 load mode command: enable write leveling and r tt(nom) odtlon + t aon + t mod + 1ck dqs, dqs# drive r tt,nom value dqs no r tt,nom mr1 load mode command: disable write leveling and r tt(nom) odtloff + t aoff + t mod + 1ck dqs, dqs# no r tt,nom dqs no r tt,nom functional description the dynamic odt mode is enabled if either mr2[9] or mr2[10] is set to 1. dynamic odt is not supported during dll disable mode so r tt(wr) must be disabled. the dy- namic odt function is described below: ? two r tt values are availabler tt,nom and r tt(wr) . C the value for r tt,nom is preselected via mr1[9, 6, 2]. C the value for r tt(wr) is preselected via mr2[10, 9]. 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 187 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
? during dram operation without read or write commands, the termination is con- trolled. C nominal termination strength r tt,nom is used. C termination on/off timing is controlled via the odt ball and latencies odtlon and odtloff. ? when a write command (wr, wrap, wrs4, wrs8, wraps4, wraps8) is registered, and if dynamic odt is enabled, the odt termination is controlled. C a latency of odtlcnw after the write command: termination strength r tt,nom switches to r tt(wr) C a latency of odtlcwn8 (for bl8, fixed or otf) or odtlcwn4 (for bc4, fixed or otf) after the write command: termination strength r tt(wr) switches back to r tt,nom . C on/off termination timing is controlled via the odt ball and determined by odt- lon, odtloff, odth4, and odth8. C during the t adc transition window, the value of r tt is undefined. odt is constrained during writes and when dynamic odt is enabled (see table 81 (page 188)). odt timings listed in table 79 (page 186) also apply to dynamic odt mode. table 81: dynamic odt specific parameters symbol description begins at defined to definition for all ddr3 speed bins unit odtlcnw change from r tt,nom to r tt(wr) write registration r tt switched from r tt,nom to r tt(wr) wl - 2 t ck odtlcwn4 change from r tt(wr) to r tt,nom (bc4) write registration r tt switched from r tt(wr) to r tt,nom 4 t ck + odtl off t ck odtlcwn8 change from r tt(wr) to r tt,nom (bl8) write registration r tt switched from r tt(wr) to r tt,nom 6 t ck + odtl off t ck t adc r tt change skew odtlcnw completed r tt transition complete 0.5 t ck 0.2 t ck t ck table 82: mode registers for r tt,nom mr1 (r tt,nom ) r tt,nom (rzq) r tt,nom (ohm) r tt,nom mode restriction m9 m6 m2 0 0 0 off off n/a 0 0 1 rzq/4 60 self refresh 0 1 0 rzq/2 120 0 1 1 rzq/6 40 1 0 0 rzq/12 20 self refresh, write 1 0 1 rzq/8 30 1 1 0 reserved reserved n/a 1 1 1 reserved reserved n/a note: 1. rzq = 240 . if r tt,nom is used during writes, only rzq/2, rzq/4, rzq/6 are allowed. 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 188 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 83: mode registers for r tt(wr) mr2 (r tt(wr) ) r tt(wr) (rzq) r tt(wr) (ohm) m10 m9 0 0 dynamic odt off: write does not affect r tt,nom 0 1 rzq/4 60 1 0 rzq/2 120 1 1 reserved reserved table 84: timing diagrams for dynamic odt figure and page title figure 103 (page 190) dynamic odt: odt asserted before and after the write, bc4 figure 104 (page 190) dynamic odt: without write command figure 105 (page 191) dynamic odt: odt pin asserted together with write command for 6 clock cycles, bl8 figure 106 (page 192) dynamic odt: odt pin asserted with write command for 6 clock cycles, bc4 figure 107 (page 192) dynamic odt: odt pin asserted with write command for 4 clock cycles, bc4 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 189 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 103: dynamic odt: odt asserted before and after the write, bc4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlon odtlcwn4 odtlcnw wl odtloff t10 t11 t12 t13 t14 t15 t17 t16 ck ck# command address r tt odt dq dqs, dqs# valid wrs4 nop nop nop nop nop nop nop dont care transitioning r tt(wr) r tt,nom r tt,nom di n + 3 di n + 2 di n + 1 di n nop nop nop nop nop nop nop nop nop nop odth4 odth4 t aon (min) t adc (min) t adc (min) t aof (min) t aon (max) t adc (max) t adc (max) t aof (max) notes: 1. via mrs or otf. al = 0, cwl = 5. r tt,nom and r tt(wr) are enabled. 2. odth4 applies to first registering odt high and then to the registration of the write command. in this example, odth4 is satisfied if odt goes low at t8 (four clocks after the write command). figure 104: dynamic odt: without write command t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtloff t10 t11 ck ck# r tt dont care transitioning command valid valid valid valid valid valid valid valid valid valid valid valid address dqs, dqs# dq odth4 odtlon t aon (max) t aon (min) t aof (min) t aof (max) odt r tt,nom notes: 1. al = 0, cwl = 5. r tt,nom is enabled and r tt(wr) is either enabled or disabled. 2. odth4 is defined from odt registered high to odt registered low; in this example, odth4 is satisfied. odt reg- istered low at t5 is also legal. 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 190 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 105: dynamic odt: odt pin asserted together with write command for 6 clock cycles, bl8 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlcwn8 odtlon odtlcnw wl t aof (max) t10 t11 ck ck# address r tt odt dq dqs, dqs# di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 valid dont care transitioning command wrs8 nop nop nop nop nop nop nop nop nop nop nop r tt(wr) odth8 odtloff t adc (max) t aon (min) t aof (min) notes: 1. via mrs or otf; al = 0, cwl = 5. if r tt,nom can be either enabled or disabled, odt can be high. r tt(wr) is enabled. 2. in this example, odth8 = 6 is satisfied exactly. 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 191 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 106: dynamic odt: odt pin asserted with write command for 6 clock cycles, bc4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlon odtlcnw wl t10 t11 ck ck# odtlcwn4 dqs, dqs# address valid dont care transitioning odtloff command wrs4 nop nop nop nop nop nop nop nop nop nop nop dq di n + 3 di n + 2 di n + 1 di n t adc (min) t aof (min) t aof (max) t adc (max) t adc (max) t aon (min) odth4 odt r tt r tt(wr) r tt,nom notes: 1. via mrs or otf. al = 0, cwl = 5. r tt,nom and r tt(wr) are enabled. 2. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. odt registered low at t5 is also legal. figure 107: dynamic odt: odt pin asserted with write command for 4 clock cycles, bc4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlon odtlcnw wl t10 t11 ck ck# odtlcwn4 dqs, dqs# address valid command wrs4 nop nop nop nop nop nop nop nop nop nop nop dont care transitioning dq di n di n + 3 di n + 2 di n + 1 odth4 t adc (max) t aon (min) t aof (min) t aof (max) odtloff r tt r tt(wr) odt notes: 1. via mrs or otf. al = 0, cwl = 5. r tt,nom can be either enabled or disabled. if disabled, odt can remain high. r tt(wr) is enabled. 2. in this example odth4 = 4 is satisfied exactly. 2gb: x4, x8, x16 ddr3 sdram dynamic odt pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 192 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked and when either r tt,nom or r tt(wr) is enabled. based on the power-down definition, these modes are: ? any bank active with cke high ? refresh mode with cke high ? idle mode with cke high ? active power-down mode (regardless of mr0[12]) ? precharge power-down mode if dll is enabled by mr0[12] during precharge power- down odt latency and posted odt in synchronous odt mode, r tt turns on odtlon clock cycles after odt is sampled high by a rising clock edge and turns off odtloff clock cycles after odt is registered low by a rising clock edge. the actual on/off times varies by t aon and t aof around each clock edge (see table 85 (page 194)). the odt latency is tied to the write latency (wl) by odtlon = wl - 2 and odtloff = wl - 2. since write latency is made up of cas write latency (cwl) and additive latency (al), the al programmed into the mode register (mr1[4, 3]) also applies to the odt signal. the devices internal odt signal is delayed a number of clock cycles defined by the al relative to the external odt signal. thus, odtlon = cwl + al - 2 and odtloff = cwl + al - 2. timing parameters synchronous odt mode uses the following timing parameters: odtlon, odtloff, odth4, odth8, t aon, and t aof. the minimum r tt turn-on time ( t aon [min]) is the point at which the device leaves high-z and odt resistance begins to turn on. maxi- mum r tt turn-on time ( t aon [max]) is the point at which odt resistance is fully on. both are measured relative to odtlon. the minimum r tt turn-off time ( t aof [min]) is the point at which the device starts to turn off odt resistance. the maximum r tt turn off time ( t aof [max]) is the point at which odt has reached high-z. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write com- mand is registered by the dram with odt high, then odt must remain high until odth4 (bc4) or odth8 (bl8) after the write command (see figure 109 (page 195)). odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low. 2gb: x4, x8, x16 ddr3 sdram synchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 193 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 85: synchronous odt parameters symbol description begins at defined to definition for all ddr3 speed bins unit odtlon odt synchronous turn-on delay odt registered high r tt(on) t aon cwl + al - 2 t ck odtloff odt synchronous turn-off delay odt registered high r tt(off) t aof cwl +al - 2 t ck odth4 odt minimum high time after odt assertion or write (bc4) odt registered high or write regis- tration with odt high odt registered low 4 t ck t ck odth8 odt minimum high time after write (bl8) write registration with odt high odt registered low 6 t ck t ck t aon odt turn-on relative to odtlon completion completion of odtlon r tt(on) see table 51 (page 71) ps t aof odt turn-off relative to odtloff completion completion of odtloff r tt(off) 0.5 t ck 0.2 t ck t ck figure 108: synchronous odt t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 cwl - 2 al = 3 al = 3 t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 ck ck# r tt odt dont care transitioning r tt,nom cke t aof (min) odtloff = cwl + al - 2 odtlon = cwl + al - 2 odth4 (min) t aon (min) note: 1. al = 3; cwl = 5; odtlon = wl = 6.0; odtloff = wl - 2 = 6. r tt,nom is enabled. 2gb: x4, x8, x16 ddr3 sdram synchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 194 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 109: synchronous odt (bc4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aof (max) t aof (min) t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck# r tt cke nop wrs4 nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop command dont care transitioning t aon (min) r tt,nom odtloff = wl - 2 odth4 (min) odth4 odtloff = wl - 2 odtlon = wl - 2 t aon (min) t aon (max) odth4 odtlon = wl - 2 t aof (min) odt r tt,nom notes: 1. wl = 7. r tt,nom is enabled. r tt(wr) is disabled. 2. odt must be held high for at least odth4 after assertion (t1). 3. odt must be kept high odth4 (bc4) or odth8 (bl8) after the write command (t7). 4. odth is measured from odt first registered high to odt first registered low or from the registration of the write command with odt high to odt registered low. 5. although odth4 is satisfied from odt registered high at t6, odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. 2gb: x4, x8, x16 ddr3 sdram synchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 195 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
odt off during reads because the device cannot terminate and drive at the same time, r tt must be disabled at least one-half clock cycle before the read preamble by driving the odt ball low (if either r tt,nom or r tt(wr) is enabled). r tt may not be enabled until the end of the post- amble, as shown in the following example. note: odt may be disabled earlier and enabled later than shown in figure 110 (page 197). 2gb: x4, x8, x16 ddr3 sdram synchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 196 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 110: odt during reads t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17 t16 ck ck# valid address di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq dqs, dqs# dont care transitioning command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read odtlon = cwl + al - 2 odt t aon (max) rl = al + cl odtloff = cwl + al - 2 t aof (min) r tt r tt,nom r tt,nom t aof (max) note: 1. odt must be disabled externally during reads by driving odt low. for example, cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtlon = cwl + al - 2 = 8; odtloff = cwl + al - 2 = 8. r tt,nom is enabled. r tt(wr) is a dont care. 2gb: x4, x8, x16 ddr3 sdram synchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 197 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous odt mode asynchronous odt mode is available when the dram runs in dll on mode and when either r tt,nom or r tt(wr) is enabled; however, the dll is temporarily turned off in pre- charged power-down standby (via mr0[12]). additionally, odt operates asynchronous- ly when the dll is synchronizing after being reset. see power-down mode (page 175) for definition and guidance over power-down details. in asynchronous odt timing mode, the internal odt command is not delayed by al relative to the external odt command. in asynchronous odt mode, odt controls r tt by analog time. the timing parameters t aonpd and t aofpd replace odtlon/ t aon and odtloff/ t aof, respectively, when odt operates asynchronously. the minimum r tt turn-on time ( t aonpd [min]) is the point at which the device termi- nation circuit leaves high-z and odt resistance begins to turn on. maximum r tt turn- on time ( t aonpd [max]) is the point at which odt resistance is fully on. t aonpd (min) and t aonpd (max) are measured from odt being sampled high. the minimum r tt turn-off time ( t aofpd [min]) is the point at which the device termi- nation circuit starts to turn off odt resistance. maximum r tt turn-off time ( t aofpd [max]) is the point at which odt has reached high-z. t aofpd (min) and t aofpd (max) are measured from odt being sampled low. 2gb: x4, x8, x16 ddr3 sdram asynchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 198 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 111: asynchronous odt timing with fast odt transition t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aonpd (max) t aofpd (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck# r tt odt r tt,nom dont care transitioning cke t ih t is t ih t is t aofpd (min) t aonpd (min) note: 1. al is ignored. table 86: asynchronous odt timing parameters for all speed bins symbol description min max unit t aonpd asynchronous r tt turn-on delay (power-down with dll off) 2 8.5 ns t aofpd asynchronous r tt turn-off delay (power-down with dll off) 2 8.5 ns 2gb: x4, x8, x16 ddr3 sdram asynchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 199 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
synchronous to asynchronous odt mode transition (power-down entry) there is a transition period around power-down entry (pde) where the drams odt may exhibit either synchronous or asynchronous behavior. this transition period oc- curs if the dll is selected to be off when in precharge power-down mode by the setting mr0[12] = 0. power-down entry begins t anpd prior to cke first being registered low, and ends when cke is first registered low. t anpd is equal to the greater of odtloff + 1 t ck or odtlon + 1 t ck. if a refresh command has been issued, and it is in progress when cke goes low, power-down entry ends t rfc after the refresh command, rath- er than when cke is first registered low. power-down entry then becomes the greater of t anpd and t rfc - refresh command to cke registered low. odt assertion during power-down entry results in an r tt change as early as the lesser of t aonpd (min) and odtlon t ck + t aon (min), or as late as the greater of t aonpd (max) and odtlon t ck + t aon (max). odt de-assertion during power-down entry can result in an r tt change as early as the lesser of t aofpd (min) and odtloff t ck + t aof (min), or as late as the greater of t aofpd (max) and odtloff t ck + t aof (max). table 87 (page 201) summarizes these parameters. if al has a large value, the uncertainty of the state of r tt becomes quite large. this is because odtlon and odtloff are derived from the wl; and wl is equal to cwl + al. figure 112 (page 201) shows three different cases: ? odt_a: synchronous behavior before t anpd. ? odt_b: odt state changes during the transition period with t aonpd (min) < odtlon t ck + t aon (min) and t aonpd (max) > odtlon t ck + t aon (max). ? odt_c: odt state changes after the transition period with asynchronous behavior. 2gb: x4, x8, x16 ddr3 sdram asynchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 200 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 87: odt parameters for power-down (dll off) entry and exit transition period description min max power-down entry transition period (power-down entry) greater of: t anpd or t rfc - refresh to cke low power-down exit transition period (power-down exit) t anpd + t xpdll odt to r tt turn-on delay (odtlon = wl - 2) lesser of: t aonpd (min) (2ns) or odtlon t ck + t aon (min) greater of: t aonpd (max) (8.5ns) or odtlon t ck + t aon (max) odt to r tt turn-off delay (odtloff = wl - 2) lesser of: t aofpd (min) (2ns) or odtloff t ck + t aof (min) greater of: t aofpd (max) (8.5ns) or odtloff t ck + t aof (max) t anpd wl - 1 (greater of odtloff + 1 or odtlon + 1) figure 112: synchronous to asynchronous transition during precharge power-down (dll off) entry t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aofpd (max) odtloff t10 t11 t12 t13 ta0 ta1 ta3 ta2 ck ck# dram r tt b asynchronous or synchronous r tt,nom dram r tt c asynchronous r tt,nom dont care transitioning cke nop nop nop nop nop command nop ref nop nop nop nop nop nop nop nop nop nop nop pde transition period indicates break in time scale odtloff + t aofpd (min) t aofpd (max) t aofpd (min) odtloff + t aofpd (max) t aofpd (min) t anpd t aof (min) t aof (max) dram r tt a synchronous r tt,nom odt a synchronous odt c asynchronous odt b asynchronous or synchronous t rfc (min) note: 1. al = 0; cwl = 5; odtl(off) = wl - 2 = 3. 2gb: x4, x8, x16 ddr3 sdram asynchronous odt mode pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 201 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous to synchronous odt mode transition (power-down exit) the drams odt can exhibit either asynchronous or synchronous behavior during power-down exit (pdx). this transition period occurs if the dll is selected to be off when in precharge power-down mode by setting mr0[12] to 0. power-down exit begins t anpd prior to cke first being registered high, and ends t xpdll after cke is first reg- istered high. t anpd is equal to the greater of odtloff + 1 t ck or odtlon + 1 t ck. the transition period is t anpd + t xpdll. odt assertion during power-down exit results in an r tt change as early as the lesser of t aonpd (min) and odtlon t ck + t aon (min), or as late as the greater of t aonpd (max) and odtlon t ck + t aon (max). odt de-assertion during power-down exit may result in an r tt change as early as the lesser of t aofpd (min) and odtloff t ck + t aof (min), or as late as the greater of t aofpd (max) and odtloff t ck + t aof (max). table 87 (page 201) summarizes these parameters. if al has a large value, the uncertainty of the r tt state becomes quite large. this is be- cause odtlon and odtloff are derived from wl, and wl is equal to cwl + al. fig- ure 113 (page 203) shows three different cases: ? odt c: asynchronous behavior before t anpd. ? odt b: odt state changes during the transition period, with t aofpd (min) < odtl- off t ck + t aof (min), and odtloff t ck + t aof (max) > t aofpd (max). ? odt a: odt state changes after the transition period with synchronous response. 2gb: x4, x8, x16 ddr3 sdram asynchronous to synchronous odt mode transition (power- down exit) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 202 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 113: asynchronous to synchronous transition during precharge power-down (dll off) exit t0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 tb2 tc0 tc1 td0 td1 tc2 ck ck# dont care transitioning odt c synchronous nop nop nop command nop nop nop nop nop nop nop nop nop r tt b asynchronous or synchronous dram r tt a asynchronous dram r tt c synchronous r tt,nom nop nop odt b asynchronous or synchronous cke t aof (min) r tt,nom indicates break in time scale odtloff + t aof (min) t aofpd (max) odtloff + t aof (max) t xpdll t aof (max) odtloff odt a asynchronous pdx transition period t aofpd (min) t aofpd (max) r tt,nom t anpd t aofpd (min) note: 1. cl = 6; al = cl - 1; cwl = 5; odtloff = wl - 2 = 8. 2gb: x4, x8, x16 ddr3 sdram asynchronous to synchronous odt mode transition (power- down exit) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 203 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous to synchronous odt mode transition (short cke pulse) if the time in the precharge power-down or idle states is very short (short cke low pulse), the power-down entry and power-down exit transition periods overlap. when overlap occurs, the response of the drams r tt to a change in the odt state can be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period, even if the entry period ends later than the exit period. if the time in the idle state is very short (short cke high pulse), the power-down exit and power-down entry transition periods overlap. when this overlap occurs, the re- sponse of the drams r tt to a change in the odt state may be synchronous or asyn- chronous from the start of power-down exit transition period to the end of the power- down entry transition period. 2gb: x4, x8, x16 ddr3 sdram asynchronous to synchronous odt mode transition (power- down exit) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 204 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 114: transition period for short cke low cycles with entry and exit period overlapping t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 ta1 ta2 ta3 ta4 ck ck# cke command dont care transitioning t xpdll t rfc (min) nop nop nop nop nop nop nop nop nop nop ref nop nop nop nop pde transition period pdx transition period indicates break in time scale t anpd short cke low transition period (r tt change asynchronous or synchronous) t anpd note: 1. al = 0, wl = 5, t anpd = 4. figure 115: transition period for short cke high cycles with entry and exit period overlapping t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ck ck# command dont care transitioning nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop t anpd t xpdll indicates break in time scale ta0 ta1 ta2 ta3 ta4 cke t anpd short cke high transition period (r tt change asynchronous or synchonous) note: 1. al = 0, wl = 5, t anpd = 4. 2gb: x4, x8, x16 ddr3 sdram asynchronous to synchronous odt mode transition (power- down exit) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 205 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2gb: x4, x8, x16 ddr3 sdram asynchronous to synchronous odt mode transition (power- down exit) pdf: 09005aef826aaadc 2gb_ddr3_sdram.pdf C rev. p 2/12 en 206 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/

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